Non-planar and Planar FET Gate Integration via Shared Mask
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Solution Overview
Problem
Current planar FETs fail to meet the requirements of miniaturized electronic products due to limitations in achieving high drive current and reducing the short channel effect, and integrating non-planar FET formation methods with conventional planar FET methods is challenging, especially when forming Fin-FETs on traditional bulk-silicon substrates.
Innovation Solution
A method is developed to simultaneously form non-planar FET and planar FET gates using the same mask layer, involving the creation of very shallow trench isolations (VSTI) and conductor layers on a substrate, allowing for the formation of Fin-FETs on both active and peripheral regions, with the gates being horizontally level and precise planarization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If Fin-FET is formed on traditional bulk-silicon substrate, then high drive current and reduced short channel effect are achieved, but the forming method becomes more complicated and integration with planar FET is difficult
Solution Approach 1:
The substrate is divided into active region and peripheral region, with different FET structures formed in each region. The active region contains non-planar FETs (Fin-FETs) while the peripheral region contains planar FETs, allowing both structures to coexist on the same substrate without interfering with each other's formation processes
Solution Approach 2:
The same mask layer is used for forming both STI in the peripheral region and VSTI in the active region, streamlining the manufacturing process. The conductor layer also serves dual purposes by forming both planar FET gates and non-planar FET gates simultaneously, reducing process steps and complexity
2Manufacturing precision
If separate processes are used for STI and VSTI formation, then precise isolation is achieved, but the manufacturing process becomes more complex
Solution Approach 1:
The formation of STI and VSTI is merged into a single etching process using the same mask layer. The etching conditions are optimized to achieve different etching depths in different regions (deeper etching for VSTI in active region, shallower etching for STI in peripheral region), thereby reducing process steps while maintaining precise isolation
Data Source
AI summary
A method of forming a Non-planar FET is provided. A substrate is provided. An active region and a peripheral region are defined on the substrate. A plurality of VSTI is formed in the active region of the substrate. A part of each VSTI is removed to expose a part of sidewall of the substrate. Then, a conductor layer is formed on the substrate which is then patterned to form a planar FET gate in the peripheral region and a Non-planar FET gate in the active region simultaneously. Last, a source/drain region is formed on two sides of the Non-planar FET gate.