FET Gate Wiring Shield Layout for Lower Parasitic Capacitance
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Solution Overview
Problem
In field effect transistors (FETs) with finger-shaped electrodes, the arrangement of multiple units leads to increased gate resistance and parasitic capacitance between the gate wiring and drain electrode, deteriorating the device's characteristics such as gain.
Innovation Solution
The semiconductor device incorporates a guard metal layer between the gate wiring and drain electrode, electrically connected to the source electrode, which helps reduce parasitic capacitance and improve high-frequency characteristics without increasing the device's size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple unit FETs are arranged in the extending direction of the electrodes, then the gate resistance is reduced, but the parasitic capacitance between the gate wiring and drain electrode increases
Solution Approach 1:
A guard metal layer is introduced as an intermediary structure between the gate wiring and drain electrode. This guard metal layer acts as a shielding element that reduces the parasitic capacitance formed between the gate wiring and drain electrode, while allowing the multiple unit FETs to remain arranged in the extending direction for low gate resistance
Solution Approach 2:
The harmful parasitic capacitance effect is extracted and addressed by separating the gate wiring from the drain electrode region using the guard metal layer. This allows the beneficial arrangement of multiple unit FETs to be maintained while removing the detrimental capacitance effect
2Ease of manufacture
If the gate wiring is provided above the source electrode to connect the gate pad and second gate electrode, then the electrical connection is achieved, but the parasitic capacitance between gate wiring and drain electrode increases
Solution Approach 1:
The guard metal layer serves as a shielding intermediary positioned between the gate wiring and drain electrode. It allows the gate wiring to be routed above the source electrode for ease of manufacturing electrical connections, while simultaneously reducing the harmful parasitic capacitance through electromagnetic shielding
3Reliability
If the device size is increased to reduce parasitic capacitance, then the high-frequency characteristics improve, but the device area increases
Solution Approach 1:
The introduction of the guard metal layer changes the electromagnetic field distribution parameters in the device. By adding this shielding layer, the parasitic capacitance is reduced without requiring an increase in device area, thereby improving high-frequency characteristics while maintaining compact dimensions
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The implementation of a guard metal layer effectively suppresses the deterioration of high-frequency characteristics by reducing parasitic capacitance, allowing for improved performance without enlarging the semiconductor device.
Implementation Method 1
parasitic capacitance between the gate wiring and drain electrode
Data Source
AI summary
A semiconductor device includes a substrate, a source electrode extending, a drain electrode, a first gate electrode extending in a first direction and provided between the source electrode and the drain electrode, a second gate electrode extending in the first direction and provided on the substrate in the first direction of the first gate electrode between the source electrode and the drain electrode, a gate pad provided so as to interpose the first gate electrode between the second gate electrode and the gate pad and electrically connected to the first gate electrode, a gate wiring provided above the source electrode and electrically connecting the gate pad and the second gate electrode, and a guard metal layer provided between the gate wiring and the drain electrode, at least a part of the guard metal layer being provided above the source electrode and electrically connected to the source electrode.