Power FET Gate Voltage Slope Control for EMI and Power Loss
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Solution Overview
Problem
Switching regulators face challenges in reducing electromagnetic interference (EMI) emissions and power loss due to the rapid changes in input current when activating or deactivating a power FET, with existing solutions either increasing EMI or power loss.
Innovation Solution
A slope control circuit dynamically adjusts the rate-of-change of the gate voltage of the power FET, reducing EMI emissions by slowing the increase before activation and increasing it after full activation to minimize power loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the gate voltage of the power FET is increased rapidly to reduce power loss, then power efficiency is improved, but EMI emissions increase due to rapid current changes
Solution Approach 1:
The patent applies dynamics by making the gate voltage increase rate variable rather than fixed. The slope control circuit dynamically adjusts the gate voltage slope based on the FET's activation state: using a first slope during threshold activation and a second slope after full activation. This dynamic adjustment resolves the contradiction by applying rapid voltage increase only when necessary (after activation) to reduce power loss, while using a slower slope during threshold crossing to minimize EMI emissions.
Solution Approach 2:
The patent changes the parameter of gate voltage slope (rate of change) based on the FET's operating state. The slope control circuit monitors the FET activation state and adjusts the voltage slope parameter accordingly. This parameter change strategy allows the system to optimize between EMI reduction (slower slope at threshold) and power efficiency (faster slope after activation).
2Object-generated harmful factors
If the gate voltage increase rate is slowed to reduce EMI emissions, then EMI compliance is improved, but power loss increases due to extended freewheeling diode conduction
Solution Approach 1:
The patent segments the gate voltage increase process into two distinct phases: (1) threshold activation phase with a first slope for EMI control, and (2) full activation phase with a second slope for power efficiency. This segmentation allows each phase to be optimized independently - the first phase prioritizes EMI reduction while the second phase prioritizes power loss reduction, resolving the contradiction through temporal separation of objectives.
Solution Approach 2:
The patent implements periodic action by switching between two different voltage slopes at a specific transition point (when the FET reaches threshold activation). The slope control circuit periodically changes the voltage increase rate based on the FET's state, applying the appropriate slope for each operational phase to balance EMI and power loss considerations.
Data Source
AI summary
A system and method is provided for driving a power field-effect transistor (FET). In one embodiment, a system comprises a control circuit that generates a control signal to provide a gate voltage of the power FET. The system further comprises a slope control circuit coupled between the control circuit and the power FET that is operative to dynamically control the rate-of-change of a gate voltage of the power FET to reduce electromagnetic interference (EMI) emissions and power loss resulting from switching the power FET.