High Frequency Switch FET Gate Width Balancing
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Solution Overview
Problem
High frequency switches using semiconductors often experience deviations in insertion loss due to positional relations between the common terminal and input/output terminals, leading to differences in transmission signal quality.
Innovation Solution
The high frequency switch incorporates a semiconductor element with multiple FETs and a molded member, featuring specific configurations of signal propagation directions and gate widths to balance resistance differences across transfer paths, including zones with opposite signal propagation directions and adjusted wiring conductor lengths to minimize insertion loss deviations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a high frequency switch is formed using a semiconductor with multiple FETs, then the switch can selectively connect common terminal to multiple input/output terminals, but a deviation in insertion loss occurs among the transfer paths due to positional relations between terminals
Solution Approach 1:
The patent applies local quality by configuring different gate widths for different FETs based on their specific positional relationships with the common terminal. FETs closer to the common terminal have narrower gate widths, while those farther away have wider gate widths, creating localized adjustments that compensate for path length differences and achieve uniform insertion loss across all transfer paths.
Solution Approach 2:
The patent changes the parameter of gate width for each FET to compensate for insertion loss deviations. By adjusting the gate width parameter according to the distance from the common terminal, the resistance characteristics of each FET are optimized to balance the overall insertion loss across different transfer paths.
2Power
If the gate width of FETs is increased to reduce resistance, then the power handling capability improves, but the insertion loss deviation among different transfer paths increases
Solution Approach 1:
The patent applies local quality by configuring different gate widths for different FETs based on their specific positional relationships with the common terminal. FETs closer to the common terminal have narrower gate widths, while those farther away have wider gate widths, creating localized adjustments that compensate for path length differences and achieve uniform insertion loss across all transfer paths.
Solution Approach 2:
The patent changes the parameter of gate width for each FET to compensate for insertion loss deviations. By adjusting the gate width parameter according to the distance from the common terminal, the resistance characteristics of each FET are optimized to balance the overall insertion loss across different transfer paths.
3Loss of energy
If the gate width of FETs is decreased to reduce insertion loss, then the insertion loss decreases, but the power handling capability deteriorates
Solution Approach 1:
The patent applies local quality by configuring different gate widths for different FETs based on their specific positional relationships with the common terminal. FETs closer to the common terminal have narrower gate widths, while those farther away have wider gate widths, creating localized adjustments that compensate for path length differences and achieve uniform insertion loss across all transfer paths.
Solution Approach 2:
The patent changes the parameter of gate width for each FET to compensate for insertion loss deviations. By adjusting the gate width parameter according to the distance from the common terminal, the resistance characteristics of each FET are optimized to balance the overall insertion loss across different transfer paths.
Data Source
AI summary
A length of a zone in which a power propagation direction from an input/output terminal (P251) toward a common terminal (P20) and a power propagation direction from the common terminal (P20) toward an external connection terminal (P10) are opposite to each other is longer than a length of a zone in which a power propagation direction from an input/output terminal (P211) toward the common terminal (P20) and a power propagation direction from the common terminal (P20) toward the external connection terminal (P10) are opposite to each other. A FET (251) and a FET (211) have structures that power transferred between a drain and a source of the FET (251) in accordance with predetermined input power is greater than power transferred between a drain and a source of the FET (211).