Semiconductor FET Gate Wiring Layout for Lower Gate-Drain Capacitance
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Solution Overview
Problem
Existing semiconductor devices face challenges in suppressing gate/drain capacitance and maintaining performance characteristics while minimizing size, as conventional designs either increase parasitic capacitance or require larger chip sizes.
Innovation Solution
The semiconductor device incorporates a specific arrangement of unit FETs, source and drain electrodes, and gate wiring, where the gate wiring interposes the source wiring between the gate and drain electrodes, and the source wiring has a maximum contact width half that of its overlap width, reducing capacitance and allowing for downsizing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the gate wiring is arranged to overlap the source electrode to reduce chip size, then the chip size is reduced, but the gate/drain capacitance increases
Solution Approach 1:
The source wiring is introduced as an intermediary element positioned between the gate wiring and drain electrode. This source wiring acts as a shield that intercepts and redirects electric field lines, preventing direct capacitive coupling between the gate wiring and drain electrode. The source wiring's strategic placement creates an electromagnetic shield that reduces the harmful gate/drain capacitance while allowing the gate wiring to maintain its compact overlapping arrangement with the source electrode.
Solution Approach 2:
The patent applies local quality by creating a non-uniform electric field distribution through the strategically positioned source wiring. The source wiring is specifically placed in regions where electric field concentration would otherwise create high capacitance, providing localized shielding where it is most needed. This allows different regions of the device to have different electromagnetic characteristics - high capacitance regions are suppressed locally by the source wiring shield while maintaining overall compact dimensions.
2Object-generated harmful factors
If the gate wiring is positioned away from the drain electrode to reduce capacitance, then the gate/drain capacitance is reduced, but the chip size increases
Solution Approach 1:
The source wiring serves as an active intermediary that enables the gate wiring to be positioned closer to the drain electrode without increasing capacitance. By placing the source wiring between the gate wiring and drain electrode, it creates an electromagnetic barrier that allows compact routing while maintaining low capacitance. This intermediary structure decouples the spatial relationship between gate wiring and drain electrode from the capacitive coupling, enabling independent optimization of both parameters.
3Power
If multiple unit FETs are arranged in parallel to increase current capacity, then the current capacity is increased, but the parasitic capacitance accumulates
Solution Approach 1:
The patent segments the gate wiring into multiple separate gate wirings, each serving a specific unit FET. This segmentation prevents the formation of a large common capacitance that would occur with a single shared gate wiring. Each segmented gate wiring has its own dedicated source wiring shield, which isolates the parasitic capacitance to individual FETs rather than allowing it to accumulate across all parallel devices. This segmented approach allows current capacity to scale with the number of FETs while keeping parasitic capacitance proportional rather than cumulative.
Solution Approach 2:
Each unit FET in the parallel arrangement is provided with localized source wiring shielding specific to that FET's gate wiring. This local shielding approach ensures that the electric field management and capacitance control are optimized for each individual device rather than using a global shielding scheme. The local quality of shielding allows each FET to contribute to the total current capacity while its associated source wiring prevents parasitic capacitance from affecting other parallel FETs.
Data Source
AI summary
A semiconductor device includes a substrate, a first unit FET including first source, first drain, and first gate electrodes, a second unit FET including second source, second drain, and second gate electrodes, a first source wiring electrically contacting the first source electrode, a gate bus bar electrically connected to the first gate electrode, and interposing the first gate electrode between the gate bus bar and the second gate electrode, and a gate wiring provided above the first source electrode in non-contact with the first source electrode, and electrically connecting the gate bus bar and the second gate electrode, wherein a maximum width in a first direction of a region where the first source wiring contacts the first source electrode is ½ times or more a maximum width in the first direction of a region where the first source wiring overlaps the first source electrode.