Power FET Gate-Drive Limiting for Startup Inrush Control
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Solution Overview
Problem
Existing DC-DC power converters face issues with excessive current in-rush during startup and charge imbalance, leading to potentially damaging voltage spikes due to parasitic inductances and device mismatches, which affect reliability and require additional circuitry for protection.
Innovation Solution
Implementing a closed-loop feedback circuit and calibrated compensation circuit to control the gate voltage of power FETs, reducing gate-drive current and mitigating current spikes independently of switching frequency, device mismatches, and temperature variations, using an LDO power supply to regulate the gate voltage of power FETs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional DC-DC power converters are used without additional protection circuitry, then device complexity is reduced, but current spikes and voltage spikes occur during startup and charge imbalance, affecting reliability
Solution Approach 1:
The patent implements a self-service mechanism where the power converter automatically detects current spikes and voltage spikes during startup and charge imbalance conditions, and self-regulates by adjusting the gate voltage of power FETs through an integrated control circuit, eliminating the need for external protection circuitry while maintaining reliability
Solution Approach 2:
The patent employs feedback control by monitoring the current and voltage conditions within the power converter and dynamically adjusting the gate voltage of power FETs based on detected anomalies, enabling the system to automatically mitigate current spikes and voltage spikes without additional protection components
2Object-generated harmful factors
If gate voltage is reduced to limit current spikes, then current limiting is achieved, but power delivery capability deteriorates
Solution Approach 1:
The patent implements dynamic gate voltage adjustment where the control circuit continuously monitors operating conditions and dynamically modifies the gate voltage of power FETs in real-time, reducing gate voltage only when current spikes are detected and restoring full power delivery capability when normal operation is detected, thereby achieving current limiting without permanent power degradation
Solution Approach 2:
The patent changes the gate voltage parameter dynamically based on operating conditions, adjusting it from full power levels to reduced levels only when current spike conditions are detected, and maintaining this adaptive parameter change to prevent current spikes while preserving full power capability when needed
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively limits current spikes during startup and dynamic charge balancing, ensuring reliable operation and maintaining output voltage stability across varying conditions without additional circuitry.
Implementation Method 1
using an LDO power supply to regulate the gate voltage of power FETs
Implementation Method 2
Implementing a closed-loop feedback circuit and calibrated compensation circuit to control the gate voltage of power FETs
Data Source
AI summary
Circuits and methods that limit current through power FETs of power converter to reduce damaging current in-rush events, independent of switching frequency, device mismatches, and PVT variations. Embodiments utilize a closed-loop feedback circuit and/or a calibrated compensation circuit to regulate, substantially independent of frequency, the control voltage VGATE applied to a power FET gate. In a reduced gate-drive mode, connecting a feedback or compensation circuit to the gate of an LDO source-follower FET allows the gate voltage to be regulated to control the LDO output voltage to a final inverter coupled to the gate of a power FET so that VGATE is adjusted to provide a reduced gate-drive to the power FET; connecting to the output of the LDO allows the LDO output voltage to the final inverter to be directly regulated to adjust VGATE; connecting to the gate of the power FET allows VGATE to be directly set.