Field Effect Transistor Structure for High-Resistance Control
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Solution Overview
Problem
Conventional semiconductor devices, such as field effect transistors (FETs), face challenges in achieving controllable resistance levels above a predetermined threshold, particularly in reducing parasitic capacitance between the gate and source/drain regions, which affects the performance of vertical FETs and limits their efficiency in applications like artificial neural networks (ANNs).
Innovation Solution
The development of semiconductor devices with a specific structure that includes a source terminal, a drain terminal, and a channel region, where an energy barrier is formed between the source and channel, and a conductive gate stack is created over the channel, allowing for controlled resistance levels by modulating the energy barrier through gate voltage, enabling high resistance values suitable for use in RPU arrays for ANN applications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional FET structures are used, then device simplicity is maintained, but resistance control above 10 MΩ is not achievable
Solution Approach 1:
The source terminal is divided into two separate terminals: a first source terminal and a second source terminal. The first source terminal is connected to the first doped region, and the second source terminal is connected to the second doped region. This segmentation allows independent control and optimization of resistance characteristics, enabling resistance values above 10 MΩ to be achieved while maintaining manageable device complexity through modular architecture.
2Reliability
If parasitic capacitance between gate and source/drain regions is not reduced, then device structure remains simple, but performance in ANN applications is limited
Solution Approach 1:
A third doped region is introduced as an intermediary element between the gate and the source/drain regions. This third doped region acts as a mediator that reduces parasitic capacitance by providing electrical isolation and optimizing the charge distribution. The intermediary structure improves reliability for ANN applications by minimizing unwanted capacitive coupling while maintaining a manageable device architecture through its strategic positioning and doping profile.
3Manufacturing precision
If doping concentration in source and drain is increased, then resistance is reduced, but resistance control above threshold is limited
Solution Approach 1:
Different doping concentrations are applied to different regions of the FET structure. The first doped region, second doped region, and third doped region each have optimized doping concentrations tailored to their specific functional requirements. This local quality approach enables precise resistance control in each region, allowing the overall device to achieve resistance values above 10 MΩ while maintaining the versatility needed for various ANN applications through region-specific optimization.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables FETs with controllable resistance above 10 MΩ, enhancing the performance of ANN systems by facilitating efficient weight storage and updates in RPU arrays, thereby improving training speed and efficiency while reducing power consumption.
Implementation Method 1
field effect transistors (FETs) with controllable resistance... a conductive gate stack is formed over the channel region, allowing for controlled resistance levels by modulating the energy barrier through gate voltage
Data Source
AI summary
A method and resulting structures for a semiconductor device includes forming a source terminal of a semiconductor fin on a substrate. An energy barrier is formed on a surface of the source terminal. A channel is formed on a surface of the energy barrier, and a drain terminal is formed on a surface of the channel. The drain terminal and the channel are recessed on either sides of the channel, and the energy barrier is etched in recesses formed by the recessing. The source terminal is recessed using timed etching to remove a portion of the source terminal in the recesses formed by etching the energy barrier. A first bottom spacer is formed on a surface of the source terminal and a sidewall of the semiconductor fin, and a gate stack is formed on the surface of the first bottom spacer.