Gate-All-Around FET With Inner Spacers and Voids
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Solution Overview
Problem
Field effect transistors (FETs) experience performance and reliability issues due to strong electrical coupling between the source and drain, causing current flow even without applied voltage, which affects the overall performance and reliability of integrated devices.
Innovation Solution
The integration of inner spacers and voids between channels in FETs reduces parasitic capacitance and isolates the source and drain, achieved through the formation of a gate-all-around (GAA) FET configuration with multiple inner spacers and voids, which helps in preventing unintended electrical coupling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional FET structure is used, then device simplicity is maintained, but strong electrical coupling between source and drain causes performance and reliability issues
Solution Approach 1:
The gate is divided into multiple segments (first gate, second gate, third gate) that surround different portions of the channel. This segmentation allows independent control of electrical coupling in different regions, enabling reduced parasitic capacitance between source and drain while maintaining overall device functionality.
Solution Approach 2:
The gates are arranged in a nested configuration where the first gate surrounds a first portion of the channel, the second gate surrounds a second portion, and the third gate surrounds a third portion. This nested structure enables progressive isolation of the source and drain regions, reducing electrical coupling while maintaining a compact design.
2Reliability
If inner spacers and voids are added to reduce parasitic capacitance, then source-drain isolation is improved, but manufacturing complexity increases
Solution Approach 1:
Inner spacers are formed preliminary to the gate formation process. By establishing the spacer structure before depositing the gate materials, the patent simplifies subsequent manufacturing steps and ensures precise positioning of the spacers relative to the channel, reducing source-drain coupling while maintaining fabrication efficiency.
Solution Approach 2:
The inner spacers act as intermediary structures between the source and drain regions. These spacers provide physical and electrical isolation, mediating the interaction between source and drain to reduce parasitic capacitance while serving as alignment references for subsequent gate formation steps.
Data Source
AI summary
An integrated device that includes a substrate and a first transistor formed over the substrate. The first transistor includes a first source disposed over the substrate, a first drain disposed over the substrate, a first plurality of channels coupled to the first source and the first drain, where the first plurality of channels is located between the first source and the first drain; at least one inner spacer located between two adjacent channels from the first plurality of channels; at least two voids located between the two adjacent channels; and a first gate surrounding the first plurality of channels.