Field-Effect Transistor Insulation Groove for Lower Parasitic Capacitance
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Solution Overview
Problem
In the fabrication of field-effect transistors, direct contact between source/drain and semiconductor material layers leads to increased parasitic capacitance and gate-induced drain leakage, affecting performance and reliability.
Innovation Solution
A method involving selective oxidation or etching to form insulation grooves with low dielectric constant materials, isolating the source/drain from high-K dielectric materials, and reducing the thickness of the second semiconductor material layer to minimize parasitic capacitance and enhance reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If source and drain are formed by doping process with direct contact to semiconductor material layers, then manufacturing process is simple, but parasitic capacitance and gate-induced drain leakage increase
Solution Approach 1:
An insulating layer is introduced as an intermediary between the source/drain regions and the high-K dielectric material. This insulating layer acts as a barrier that prevents direct contact, thereby reducing parasitic capacitance and gate-induced drain leakage while maintaining the simplicity of the doping process for source and drain formation.
Solution Approach 2:
The structure is segmented by introducing a distinct insulating layer that separates the source/drain regions from the high-K dielectric material. This segmentation creates independent functional zones, allowing the source/drain to be formed through simple doping while the insulating layer independently manages the parasitic effects.
2Reliability
If high-K dielectric material is used for gate, then gate control is improved, but parasitic capacitance increases due to direct contact with source/drain
Solution Approach 1:
The insulating layer serves as a mediator between the high-K dielectric material and the source/drain regions. It allows the high-K dielectric to maintain its superior gate control capabilities while simultaneously blocking the harmful parasitic capacitance effects that would otherwise arise from direct contact between the gate stack and source/drain.
3Device complexity
If source and drain are in direct contact with semiconductor material layers, then device structure is simple, but gate-induced drain leakage increases
Solution Approach 1:
The insulating layer is positioned as an intermediary that blocks the path for gate-induced drain leakage current. It prevents the high-K dielectric material from directly contacting the source/drain regions, thereby eliminating the mechanism that generates GIDL while adding minimal complexity to the overall device structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively reduces parasitic capacitance and improves the performance and reliability of field-effect transistors by isolating the source/drain from high-K dielectric materials and adjusting the semiconductor layer thickness.
Implementation Method 1
removing, along a gate length direction, an area other than a sacrificial layer in the first semiconductor material layer to form an insulation groove
Data Source
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AI summary
Embodiments of the present invention relate to the field of semiconductor technologies and provide a field-effect transistor and a fabrication method of a field-effect transistor, to reduce a parasitic parameter of a field-effect transistor, thereby improving reliability of the field-effect transistor. The method includes: forming a support structure (61) with a superlattice feature on a semiconductor substrate (51), where the support structure (61) includes a first semiconductor material layer (52) and a second semiconductor material layer (53) that are alternately disposed, and an isolation layer (71) is disposed on two sides of the support structure (61); forming, along a boundary between the isolation layer (71) and the support structure (61), a dummy gate structure (81) that covers the support structure (61), where a length of the dummy gate structure (81) in a gate length direction is less than a length of the first semiconductor material layer in the gate length direction; removing, along the gate length direction, an area other than a sacrificial layer (102) in the first semiconductor material layer (52) to form an insulation groove (101), where a dielectric constant of a dielectric filled in the insulation groove (101) is less than a dielectric constant of the first semiconductor material layer (52); and forming a source (131) and a drain (132) in a preset source drain area along the gate length direction, where the source (131) and the drain (132) are isolated from the sacrificial layer (102) through the insulation groove (101).