FET Interconnect Adhesion Sheath for Low Resistance
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Solution Overview
Problem
The shrinking linewidth and channel length of CMOS-compatible semiconductor devices, such as planar metal-oxide-semiconductor field effect transistors (FETs) and non-planar fin-type field effect transistors (FinFETs), pose challenges in forming metal contacts or interconnects, especially for high integration and tight design rules.
Innovation Solution
The manufacturing process involves forming a gate stack structure on a substrate with source and drain regions, using a dielectric layer and conductive region, and creating interconnect structures through sequential deposition and etching of liner, inter-dielectric, and adhesion layers, followed by metal filling and planarization, which includes the formation of a stop layer, barrier layer, and adhesion layer to control etching profiles and reduce contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the linewidth and channel length are scaled down to achieve high integration, then the device density and integration level are improved, but the formation of metal contacts and interconnects becomes more difficult and unreliable
Solution Approach 1:
The interconnect structure is divided into multiple functional layers: a barrier layer (e.g., tantalum nitride or tungsten nitride) to prevent metal diffusion, an adhesion layer (e.g., titanium nitride) to ensure metal-dielectric bonding, and the metal fill layer. This segmentation allows each layer to optimize its specific function, improving overall reliability despite scaled dimensions
Solution Approach 2:
The barrier and adhesion layers are deposited beforehand before metal filling. The barrier layer is formed first to prevent metal diffusion into the dielectric, followed by the adhesion layer to ensure proper metal bonding. This preliminary preparation ensures reliable interconnect formation even at reduced linewidths and channel lengths
2Ease of manufacture
If conventional metal contact formation is used at scaled dimensions, then the manufacturing process remains simple, but the contact resistance increases and reliability decreases
Solution Approach 1:
The interconnect structure uses composite material layers combining different properties: the barrier layer (tantalum nitride or tungsten nitride) provides diffusion protection, the adhesion layer (titanium nitride) provides bonding capability, and the metal layer provides low resistance. This composite approach reduces contact resistance while maintaining manufacturing feasibility through sequential deposition and filling processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of reliable and high-performance interconnects with lower contact resistance and improved reliability by suppressing issues like 'tiger teeth' and allowing for smaller interconnect dimensions without compromising reliability, enhancing the electrical performance of FET devices.
Implementation Method 1
A metal material is formed over the second resist pattern and the second inter-dielectric layer and fills the trench opening and the via opening
Data Source
AI summary
A field effect transistor comprising a substrate, at least one gate stack structure, source and drain regions and an interconnect structure is described. The interconnect structure comprises a metal interconnect connected to a conductive region, an adhesion sheath structure and a cap layer. The adhesion sheath structure is disposed between the metal interconnect and inter-dielectric layers and surrounds the metal interconnect. The cap layer is disposed on the metal interconnect and covers a gap between the metal interconnect and the inter-dielectric layer.