Bulk FET Sub-Source/Drain Isolation via Selective Oxidation

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Solution Overview

Problem

Ground plane doping in bulk semiconductor substrates is insufficient to prevent through-substrate source-to-drain leakage in fin-type and nanowire field effect transistors as device sizes continue to scale, impacting device on-off characteristics.

Innovation Solution

A method of forming semiconductor structures with non-planar field effect transistors, including fin-type and nanowire FETs, involves forming semiconductor fins and layers, creating recesses, and performing an oxidation process to form oxide layers, which are then selectively removed to create local isolation layers that electrically and physically separate source/drain regions from the substrate, minimizing leakage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If ground plane doping is used in bulk semiconductor substrates to prevent source-to-drain leakage, then device scalability is improved, but leakage prevention becomes insufficient as device sizes continue to scale

Engineering Contradiction:
Improveleakage preventionVSAvoiddevice scalability
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent divides the substrate into multiple regions by forming local isolation layers between source and drain regions. These isolation layers segment the continuous substrate into isolated zones, preventing leakage paths while maintaining scalability. The segmentation approach allows each region to be independently optimized for different device sizes and configurations.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies local isolation layers only in specific regions where leakage prevention is needed, rather than uniformly doping the entire substrate. This local quality approach places isolation structures precisely at source-to-drain interfaces, providing targeted leakage prevention that adapts to varying device geometries and scaling requirements.

Inventive Principle:
Principle #3Local quality

2Reliability

If local isolation layers are formed to prevent through-substrate source-to-drain leakage, then leakage prevention is improved, but device complexity increases

Engineering Contradiction:
Improvethrough-substrate leakage preventionVSAvoidisolation layer structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent forms local isolation layers during the early stages of device fabrication, before source and drain regions are fully defined. This preliminary action establishes the isolation framework in advance, simplifying subsequent processing steps and reducing overall device complexity despite the additional isolation structures.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The local isolation layers act as intermediary structures between the substrate and source-drain regions. These intermediary layers provide a simple, uniform material barrier that mediates the interaction between doped regions, preventing direct leakage paths without requiring complex multi-layer isolation systems.

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively prevents through-substrate and sub-channel region source-to-drain leakage, enhancing the on-off characteristics of the transistors by providing robust electrical isolation.

Implementation Method 1

An oxidation process can then be performed to form oxide layers on exposed semiconductor surfaces.

Methodology Applied
Scientific EffectOxidation: Oxidation

Data Source

PatentUS10580897B2Methods of forming a bulk field effect transistor (FET) with sub-source/drain isolation layers and the resulting structures
Publication Date: 2020.03.03 GLOBALFOUNDRIES US INC
  • US10580897B2 patent drawing
  • US10580897B2 patent drawing
  • US10580897B2 patent drawing

AI summary

Disclosed are structures (e.g., a fin-type field effect transistor (FINFET) and a nanowire-type FET (NWFET)) and methods of forming the structures. In the methods, a fin is formed. For a FINFET, the fin includes a first semiconductor material. For an NWFET, the fin includes alternating layers of first and second semiconductor materials. A gate is formed on the fin. Recesses are formed in the fin adjacent to the gate and extend to (or into) a semiconductor layer, below, made of the second semiconductor material. An oxidation process forms oxide layers on exposed semiconductor surfaces in the recesses including a first oxide material on the first semiconductor material and a second oxide material on the second semiconductor material. The first oxide material is then selectively removed and source/drain regions are formed by lateral epitaxial deposition in the recesses. The remaining second oxide material minimizes sub-channel region source-to-drain leakage.