FET Latching Wake-Up Circuit for Low-Power Automotive MCUs
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Solution Overview
Problem
Existing wake-up circuits for processors require dedicated signal lines, continuous power to maintain hot standby, and complex logic gate arrangements, which are costly and power-intensive.
Innovation Solution
An apparatus that uses an analog signal to wake up a processor without requiring a dedicated signal line or continuous power, employing field effect transistors (FETs) and switches to control power delivery and implement a controlled sleep cycle based on battery voltage levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a processor is kept in hot standby to respond to wake-up signals, then the system can respond quickly to activation, but continuous power is consumed
Solution Approach 1:
The system dynamically transitions the processor between sleep mode and active state based on wake-up signals. The FET-based circuit enables the processor to be completely powered down when not in use, then rapidly activated when needed, optimizing the balance between response speed and power consumption.
Solution Approach 2:
The wake-up circuit uses FETs configured to detect activation signals before the processor needs to be fully operational. The circuit prepares the power delivery path in advance through the FET network, enabling rapid processor activation without maintaining continuous power supply.
2Reliability
If dedicated signal lines are used to wake up a processor, then the wake-up function is reliable, but the circuit complexity and cost increase
Solution Approach 1:
The FET-based wake-up circuit can be integrated into existing power delivery infrastructure, allowing the same circuitry to serve both power management and wake-up detection functions. This eliminates the need for separate dedicated wake-up signal lines while maintaining reliability.
Solution Approach 2:
The circuit combines the wake-up signal detection, power control, and processor activation functions into a single integrated FET-based network. This merging of functions reduces the number of separate components and signal lines required, simplifying the overall system architecture.
3Ease of operation
If complex logic gate arrangements are used for wake-up circuits, then the wake-up control is precise, but additional power and cost are required
Solution Approach 1:
The patent replaces traditional logic gate-based control circuits with a FET-based analog control system. The FETs use voltage-controlled resistance to precisely regulate power delivery to the processor, eliminating the need for complex digital logic gates while maintaining or improving control precision.
Solution Approach 2:
The FET-based circuit controls processor activation by changing voltage parameters rather than using complex logic state transitions. The gate voltage applied to the FETs directly controls the power flow, providing precise control with simpler circuitry and lower power consumption compared to logic gate arrangements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution eliminates the need for dedicated signal lines and continuous power, reduces power consumption, and simplifies the circuit design, while enabling efficient wake-up and sleep operations based on battery voltage thresholds.
Implementation Method 1
a first field effect transistor (FET) with a gate in electrical communication with the input line; a first switch configured to be controlled by a source of the first FET
Data Source
AI summary
An apparatus for waking up a microcontroller based on an analog signal superimposed on a low voltage differential signal line in an automobile. The apparatus is realized using a pair of FETs and switches arranged to act as a latching circuit when a sufficient analog signal is detected and remains present even when the signal drops below a wake up threshold. The gate voltage threshold of the pair of FETs may be selected to control the voltage where latching does and does not occur. The apparatus also triggers a sleep cycle in the microcontroller if the signal drops below a threshold voltage. The microcontroller may be programmed to perform a controlled shutdown and terminate its power via the apparatus when finished.