FinFET Epitaxial Channel Lattice Shift for Density and Mobility
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Solution Overview
Problem
Conventional planar FETs face challenges such as sub-threshold swing degradation, significant drain-induced barrier lowering, and fluctuation of device characteristics when reduced in size, necessitating the development of more efficient semiconductor structures.
Innovation Solution
The formation of fin field-effect transistors (finFETs) and vertical channel FETs (VCFETs) through a series of manufacturing steps, including epitaxial growth, re-shaping of fins, and formation of gate dielectric and gate electrodes, to enhance device performance and density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If planar FETs are reduced in size to increase density, then device footprint is reduced, but sub-threshold swing degradation and drain-induced barrier lowering occur
Solution Approach 1:
The patent transitions from planar (2D) channel structure to vertically-oriented (3D) finFET and VCFET structures. This dimensional change allows the channel to extend vertically into the substrate, increasing the effective channel area and density without proportionally reducing the footprint, while maintaining electrical characteristics through the vertical geometry that reduces DIBL and sub-threshold swing issues
2Reliability
If fin structures are formed to improve electrical characteristics, then device performance is enhanced, but manufacturing complexity increases
Solution Approach 1:
The manufacturing process is divided into distinct sequential stages: epitaxial growth of semiconductor layers, formation of sacrificial mandrels, deposition of spacer materials, and selective removal steps. Each stage creates a specific structural feature that builds upon the previous stage, making the complex finFET fabrication process more manageable and controllable through systematic segmentation
3Productivity
If vertical channel structures are implemented to increase density, then footprint is reduced, but surface roughness and mobility issues arise
Solution Approach 1:
The patent employs precise control of epitaxial growth parameters including temperature, pressure, gas flow rates, and precursor ratios to achieve smooth fin surfaces. By optimizing these process parameters, the vertical channel structures maintain low surface roughness despite their high-density three-dimensional geometry, ensuring good electrical mobility
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
These structures improve electrical characteristics and performance by reducing surface roughness and enhancing mobility, addressing the limitations of planar FETs, particularly in high-density and low-footprint semiconductor applications.
Implementation Method 1
epitaxial growth, re-shaping of fins
Data Source
AI summary
FETs and methods for forming FETs are disclosed. A structure comprises a substrate, a gate dielectric and a gate electrode. The substrate comprises a fin, and the fin comprises an epitaxial channel region. The epitaxial channel has a major surface portion of an exterior surface. The major surface portion comprising at least one lattice shift, and the at least one lattice shift comprises an inward or outward shift relative to a center of the fin. The gate dielectric is on the major surface portion of the exterior surface. The gate electrode is on the gate dielectric.