FET Layout With STI Corner Isolation for Low Flicker Noise
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Solution Overview
Problem
Flicker noise and random telegraph noise (RTN) in field-effect transistors (FETs) are caused by defect states at the corners of shallow trench isolation structures, leading to high mechanical stress and strong electric fields, which trap and de-trap charge carriers, resulting in noise generation.
Innovation Solution
The source/drain regions are positioned away from the STI corners by using the gate electrode as a mask, and a silicide blocking structure is employed to prevent short circuits, while the gate is designed to not overlap the STI corners, reducing charge carrier trapping and de-trapping at these defect states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the source/drain regions are positioned close to the STI corners to maximize device area, then the device area is increased, but flicker noise and RTN increase due to charge carrier trapping at defect states
Solution Approach 1:
The gate electrode is used as a mask to extract or remove the harmful interaction between charge carriers and defect states at the STI corners. By positioning the gate to overlap the STI corners, the source/drain regions are naturally pushed away from these defect-prone areas, effectively separating the charge carrier paths from the harmful defect states while maintaining maximum device area.
Solution Approach 2:
The gate electrode serves as an intermediary element that mediates between the source/drain regions and the STI corners. The gate's strategic positioning creates an electric field configuration that prevents charge carriers from interacting with defect states at the STI corners, acting as a protective barrier without reducing the active device area.
2Ease of manufacture
If the gate overlaps the STI corners to simplify fabrication, then manufacturing is easier, but charge carrier trapping increases leading to higher noise
Solution Approach 1:
The gate electrode's overlap with the STI corners, which would normally be expected to cause harm by creating strong electric fields at defect locations, is converted into a benefit. This overlap configuration actually protects the source/drain regions from the harmful effects by using the gate's electric field to repel charge carriers away from the defect states at the STI corners during operation.
3Object-generated harmful factors
If source/drain regions are positioned away from STI corners using gate as mask, then noise is reduced, but device area is reduced
Solution Approach 1:
The gate electrode performs multiple functions simultaneously: it serves as the control electrode for the FET operation, acts as a mask to position source/drain regions away from STI corners during fabrication, and creates an electric field configuration that protects against charge carrier trapping. This multi-functionality achieves noise reduction without sacrificing device area.
Data Source
AI summary
In some embodiments, a semiconductor device is provided. The semiconductor device includes an isolation structure disposed in a semiconductor substrate, where an inner perimeter of the isolation structure demarcates a device region of the semiconductor substrate. A gate is disposed over the device region, where an outer perimeter of the gate is disposed within the inner perimeter of the isolation structure. A first source/drain region is disposed in the device region and on a first side of the gate. A second source/drain region is disposed in the device region and on a second side of the gate opposite the first side. A silicide blocking structure partially covers the gate, partially covers the first source/drain region, and partially covers the isolation structure, where a first sidewall of the silicide blocking structure is disposed between first opposite sidewalls of the gate.