Photoresist Mask Reuse for FET LDD Formation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The integration of field-effect transistors and other devices on the same substrate poses manufacturing challenges due to different fabrication parameters required for memory cells and non-memory devices, such as high-speed transistors and analog devices, which affect cost, performance, and reliability.
Innovation Solution
A method involving the reuse of a photoresist mask for high energy implantation to form lightly doped source and drain regions of complementary conductivity types without the need for a hard mask, allowing for the formation of high voltage gates in semiconductor devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a hard mask is used to protect poly during high energy implantation, then implantation precision is improved, but device complexity and manufacturing steps increase
Solution Approach 1:
The patent extracts and removes the hard mask layer from the manufacturing process. Instead of using a hard mask to protect poly during high energy implantation, the method relies on the photoresist mask alone, eliminating the need for hard mask deposition, patterning, and removal steps while maintaining implantation precision through careful photoresist design and process control
Solution Approach 2:
The photoresist mask is given multiple functions: it serves as both the etch mask for defining transistor gates and as the protection layer during subsequent high energy implantation steps. This multi-functional use of the photoresist mask eliminates the need for separate hard mask layers, reducing manufacturing complexity while maintaining precision
2Productivity
If multiple types of transistors are integrated on the same substrate, then productivity is improved, but manufacturing precision deteriorates due to different fabrication parameters
Solution Approach 1:
The patent applies local quality by using different photoresist materials or processing conditions in different regions of the substrate. Memory cell regions use photoresist with properties optimized for their fabrication parameters, while peripheral logic regions use photoresist tailored to their requirements, allowing each region to be manufactured with optimal precision despite integration on the same substrate
Solution Approach 2:
The substrate is segmented into different regions (memory cells and peripheral logic) that can be processed with region-specific photoresist parameters. This segmentation allows independent optimization of fabrication parameters for each device type while maintaining overall integration on a single substrate
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the simultaneous fabrication of memory and non-memory devices on the same substrate, improving manufacturing efficiency and reducing costs by eliminating the need for a hard mask, while maintaining performance and reliability.
Implementation Method 1
a high energy implantation is performed in alignment with the photoresist mask
Data Source
AI summary
Embodiments described herein generally relate to methods of manufacturing n-type lightly doped drains and p-type lightly doped drains. In one method, photoresist mask is used to etch a transistor, and the mask is left in place (i.e., reused) to protect other devices and poly while a high energy implantation is performed in alignment with the photoresist mask, such that the implantation is adjacent to the etched transistor. One example of a high energy implantation is forming lightly doped source and dram regions. This technique of reusing a photoresist mask can be employed for creating lightly doped source and drain regions of one conductivity followed by using the technique a second time to create lightly doped source and drain regions of the complementary conductivity type. This may prevent use of at least one hard mask during manufacturing.