Fin Field Effect Transistor Fabrication via Lithography Extraction
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Solution Overview
Problem
Current methods for fabricating fin field effect transistors face challenges in achieving smaller dimensions due to limitations in lithographic techniques, leading to surface roughness and poor electrical performance.
Innovation Solution
A method involving a semiconductor substrate with a fin structure between trenches, using shallow trench isolations and a gate electrode perpendicular to the fin, along with a gate dielectric layer and source/drain electrodes, is developed to improve electrical performance and reduce process complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If RIE technique is used to trim down silicon fin from overdefined size, then fin width can be reduced to desired dimension, but surface roughness is generated leading to poor electrical performance
Solution Approach 1:
The harmful RIE trimming step is completely removed from the process. Instead of forming fins at the final desired width and then trimming them, the patent extracts the trimming operation and replaces it with direct formation of fins at the correct width using lithography patterns, thereby eliminating the source of surface roughness while achieving the required dimensional precision.
Solution Approach 2:
The fin width is predetermined and defined during the initial lithography patterning step rather than being trimmed later. The lithography pattern is designed to directly create the final fin dimensions, so the fin structure is formed at its ultimate size from the beginning, preventing any subsequent roughening operations.
2Ease of manufacture
If standard lithographic technique is used to form fin structure, then process is simple, but fin width cannot be reduced below resolution limit
Solution Approach 1:
The patent transitions from planar lithography to three-dimensional fin structure formation. By forming fins that extend vertically from the substrate surface, the effective manufacturing precision is improved because the critical dimensions can be controlled through the vertical etching process rather than being limited by lateral lithographic resolution alone.
Solution Approach 2:
The patent changes the controlling parameter for fin width from lateral lithographic dimensions to a combination of lithographic pattern size and vertical etch depth. By controlling the etch process parameters and the relationship between lithography pattern dimensions and fin geometry, sub-lithographic precision is achieved through the dimensional transformation from 2D pattern to 3D structure.
3Manufacturing precision
If lithographic resolution is increased to form smaller fins, then fin width can be reduced, but process complexity increases
Solution Approach 1:
Instead of trying to directly pattern fins at sub-lithographic dimensions through increasingly complex lithography, the patent inverts the approach: it uses standard lithography to create larger patterns and then uses controlled etching to transform these into the final sub-lithographic fin dimensions. This reverses the traditional flow from direct patterning to indirect formation through transformation.
Data Source
AI summary
Methods for manufacturing semiconductor structures are provided. The method includes forming a first masking layer over a substrate and forming a second masking layer over the first masking layer. The method includes forming a photoresist pattern over the second masking layer and patterning the second masking layer through the photoresist pattern. The method further includes diminishing the photoresist pattern and patterning the second masking layer and the first masking layer through the diminished photoresist pattern. The method further includes removing the diminished photoresist pattern and patterning the semiconductor substrate through the second masking layer and the first masking layer to form a fin structure. The method further includes forming a gate structure over the fin structure.