Load Detection Circuit for FET Open-Circuit Diagnosis
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Solution Overview
Problem
Existing field effect transistor (FET) control circuits face inaccuracies in assessing system conditions due to unpredictable load impedance and power rail stability, particularly in detecting open circuits or under-load conditions.
Innovation Solution
A load detection circuit and method that operate in two modes: a first mode to form a load current and a second mode to detect the absence of a load by controlling transistors and applying specific control signals, allowing for accurate detection of load presence or absence even with leakage currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If diagnostic circuits are used to determine the state of the load, then system reliability is improved, but measurement precision deteriorates due to inaccurate assessment of system conditions
Solution Approach 1:
The circuit performs preliminary actions by disabling the FET and activating a diagnostic transistor before making the load presence determination. This preliminary action allows the circuit to establish known conditions (zero load current when FET is disabled) and then compare against these conditions to accurately detect load presence, resolving the measurement precision issue while maintaining reliability
Solution Approach 2:
The diagnostic transistor serves as an intermediary device that copies the load current path without actually carrying the load current itself. By using this intermediary transistor with matched characteristics, the circuit can accurately sense load conditions without being affected by the unpredictable load impedance and power rail variations that plague direct measurement approaches
2Measurement precision
If FET is disabled for diagnostic purposes, then measurement precision is improved, but productivity deteriorates due to interruption of normal operation
Solution Approach 1:
The circuit implements periodic diagnostic checks by enabling the diagnostic transistor at specific intervals rather than continuously. The control circuit periodically switches between normal FET operation and diagnostic measurement modes, allowing accurate load detection while minimizing interruption to productivity. This periodic action resolves the contradiction by making the FET disabled state temporary and scheduled rather than continuous
Solution Approach 2:
The diagnostic measurement is performed as a preliminary check before making operational decisions. By quickly disabling the FET, performing the load presence determination, and then re-enabling it if appropriate, the circuit minimizes the time the FET remains disabled. This preliminary action approach ensures measurement precision is achieved while the duration of productivity interruption is kept to a minimum
Data Source
AI summary
In one embodiment, a load detection circuit may include a first circuit configured to control a first transistor to form a load current to a load in a first operating mode of the load detection circuit, a second circuit configured to be coupled to form at least a portion of the load current in a second operating mode of the load detection circuit, and a detection circuit configured to detect the control electrode of the first transistor having a value that is less than a threshold value of the first transistor.