FET Local Isolation Layers on S/D Trench Sidewalls
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Solution Overview
Problem
The manufacturing of semiconductor devices faces challenges with short channel effects (SCEs) and source to drain punch due to decreasing critical dimensions, which affect device performance and increase leakage current, especially when channel length approaches the width of depletion regions, limiting further miniaturization and increasing production costs.
Innovation Solution
The method involves forming isolation layers between doping regions, using offset sidewall spacers as etching masks to create trenches, and forming filling layers with raised source/drain regions to prevent diffusion and reduce junction depth, thereby addressing short channel effects and source to drain punch.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the channel length is reduced to improve integration level and lower production cost, then the quantity of semiconductor devices in unit area increases, but short channel effects worsen and device performance deteriorates
Solution Approach 1:
The patent applies local quality by forming isolation layers specifically on the trench sidewalls adjacent to the gate structure, while leaving other regions without such layers. This localized approach addresses short channel effects in critical areas without unnecessarily complicating the entire device structure, thereby improving device performance in high-density integration scenarios.
Solution Approach 2:
The patent segments the semiconductor device structure by dividing it into regions with and without isolation layers. The trenches are formed between adjacent gate structures, and isolation layers are selectively applied to specific trench sidewalls, creating distinct functional zones that manage short channel effects locally while maintaining overall device integration.
2Productivity
If the channel length is reduced to increase device density, then manufacturing cost decreases, but offset current increases and source to drain punch occurs
Solution Approach 1:
Isolation layers are formed locally on trench sidewalls in regions where offset current and source to drain punch are most problematic. This targeted approach suppresses harmful electrical effects at critical interfaces between doping regions and substrates, reducing offset current without adding unnecessary complexity to low-density regions.
Solution Approach 2:
The isolation layers act as intermediary structures between the doping regions and the semiconductor substrate. These intermediate layers prevent direct interaction that would otherwise cause source to drain punch and excessive offset current, mediating the electrical behavior at the critical trench regions while allowing the device to maintain high density.
3Reliability
If isolation layers are formed on trench sidewalls to prevent diffusion, then junction depth is reduced and breakdown voltage increases, but device complexity increases
Solution Approach 1:
Rather than forming isolation layers on all trench sidewalls throughout the device, the patent applies them selectively only on sidewalls adjacent to the gate structure where diffusion control is most critical. This localized strategy achieves the necessary junction depth control and breakdown voltage improvement without unnecessarily increasing overall device complexity.
Solution Approach 2:
The patent segments the isolation layer formation to specific critical regions rather than applying it uniformly. By dividing the trench structures into those requiring isolation layers (adjacent to gates) and those that do not, the solution achieves reliable diffusion control and improved breakdown voltage while minimizing the added structural complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively prevents short channel effects and source to drain punch, improving semiconductor device reliability and performance by reducing resistance and increasing breakdown voltage, while enabling further device miniaturization and optimizing electrical properties.
Implementation Method 1
forming isolation layers on side surfaces of the trenches to prevent diffusions between subsequently formed doping regions
Implementation Method 2
forming trenches in the semiconductor substrate at outside of the gate structure by etching the semiconductor substrate using the offset sidewall spacers as an etching mask
Data Source
AI summary
A method is provided for fabricating a semiconductor device. The method includes providing a semiconductor substrate having a gate structure; and forming offset sidewall spacers around the gate structure. The method also includes forming trenches in the semiconductor substrate at outside of the gate structure; and forming isolation layers on side surfaces of the trenches to prevent diffusions between subsequently formed doping regions. Further, the method includes removing at least portions of the offset sidewall spacers to expose portions of the surface of the semiconductor substrate between the gate structure and the trenches; and forming filling layers with a top surface higher than the surface of the semiconductor substrate by filling the trenches and covering portions of the surface of the semiconductor substrate between the trenches and the gate structure. Further, the method also includes forming doping regions configured as raised source/drain regions in the filling layers.