Field Effect Transistor Off-Current Reduction via Voltage Stress
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Solution Overview
Problem
Field effect transistors, particularly those using amorphous or polycrystalline silicon, suffer from high OFF-current due to defects in the silicon active layer, which decreases device reliability and increases leakage currents, making it challenging to maintain the desired ON-state.
Innovation Solution
A method and system that apply a combination of DC and AC voltage pulses to the electrodes of a field effect transistor to generate an OFF-stress near the source and drain junctions, reducing defects in the silicon active layer by controlling the potential differences between the electrodes, thereby reducing OFF-current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If amorphous silicon is used for the active layer, then the transistor can be easily deposited over large areas under low temperatures, but many localized defects occur due to disordered atomic arrangement, increasing OFF-current
Solution Approach 1:
The patent applies voltage stress parameters (DC and AC voltage pulses) to change the electrical state of the junction regions, reducing defect impact without changing the physical structure or material deposition process
Solution Approach 2:
The patent uses electrical field patterns (voltage pulses) to create equivalent stress conditions that mimic the effect of perfect crystal structure, compensating for atomic-level defects through field-induced carrier redistribution
2Speed
If polycrystalline silicon is used for the active layer, then electric mobility is 100 times faster than amorphous silicon, but large amounts of leakage currents occur due to trap boundaries of crystal grains, increasing OFF-current
Solution Approach 1:
The patent applies different voltage stress conditions to different regions (source and drain junctions receive AC voltage pulses while other regions maintain DC bias), locally addressing the grain boundary trap issues at junction interfaces without affecting the bulk mobility
Solution Approach 2:
The patent applies voltage stress treatment in advance to reduce the impact of grain boundary traps before they significantly degrade device performance, preventing OFF-current buildup rather than correcting it after occurrence
3Reliability
If dual gate or multi-gate structure is used, then OFF-current problems can be overcome, but device complexity increases
Solution Approach 1:
The patent replaces structural complexity (multiple physical gates) with electrical field control (voltage pulse application), using temporal field variation instead of spatial structural multiplication to achieve the same OFF-current suppression effect
4Reliability
If AC voltage pulses are applied to generate OFF-stress, then OFF-current is reduced, but additional processing steps and time are required
Solution Approach 1:
The patent uses periodic AC voltage pulses applied during specific time windows (during device operation or formation) to generate cumulative stress effects that reduce OFF-current, leveraging repeated cyclic stress rather than continuous application to minimize time loss
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed method effectively reduces OFF-current by generating an OFF-stress near the junctions, improving the reliability of field effect transistors by minimizing leakage currents and enhancing the ON-state performance without altering the transistor structure.
Implementation Method 1
A voltage is applied to the gate electrode 8 of the field effect transistor, carriers are driven into the channel region 3
Implementation Method 2
generating an OFF-stress to each junction region using two AC (alternating current) voltage pulses to overcome the defects of the silicon active layer
Data Source
AI summary
A method for reducing an off-current of a field effect transistor in which two electrodes of the field effect transistor have fixed voltage values and the rest electrode has an alternating voltage value by an AC voltage pulse generator to form an off-stress near source and drain junctions in turn.