FET Device Forming With Offset Gate Body
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Solution Overview
Problem
Current transistor technologies face limitations in further scaling of contacted poly pitch (CPP) due to constraints in gate length, source/drain contact area, and gate spacer width, hindering the miniaturization of field-effect transistor (FET) devices.
Innovation Solution
A method for forming a field-effect transistor device with a unique design that allows for reduced CPP scaling by forming a common gate body portion laterally offset with respect to the source and drain body portions, and using a mask line to facilitate self-aligned etching of source, drain, and gate trenches, enabling the reduction or omission of the spacer between the gate and source/drain terminals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional FET design with spacer separation is used, then electrical separation between gate and source/drain is sufficient, but contacted poly pitch (CPP) cannot be further scaled below 50 nm
Solution Approach 1:
The patent transitions from planar spacer-based separation to three-dimensional offset arrangement where the gate body is laterally offset from the source/drain bodies. This dimensional change allows electrical separation without requiring lateral spacers, enabling CPP scaling below 50 nm while maintaining adequate isolation through vertical and lateral positioning in the stacked configuration.
Solution Approach 2:
The patent removes the traditional spacer structure that physically separates gate and source/drain in conventional FETs. By extracting this intermediate element and replacing it with direct offset positioning, the design eliminates the spacer width constraint that limited CPP scaling, achieving tighter pitch without compromising electrical separation.
2Length of moving object
If gate length is reduced for scaling, then transistor footprint decreases, but manufacturing precision and electrical separation become compromised
Solution Approach 1:
As gate length reduces for scaling, the patent employs the offset arrangement in the lateral dimension to maintain electrical separation. The gate body's lateral offset from source/drain bodies provides isolation that is independent of gate length, allowing continued scaling without compromising manufacturing precision or electrical separation even as dimensions shrink.
3Reliability
If chemical doping is used to maintain device performance, then electrical separation degrades and sub-threshold-swing increases, but device performance is maintained
Solution Approach 1:
The patent extracts the need for heavy chemical doping by implementing the offset body arrangement. This structural solution provides inherent electrical separation that maintains device performance without relying on dopant-induced effects, thereby eliminating the harmful sub-threshold-swing degradation and short-channel effects that accompany chemical doping.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the fabrication of FET devices with reduced spacer length, allowing for further CPP scaling and improved electrical separation, which enhances device performance and reduces the need for chemical doping, thereby minimizing sub-threshold-swing degradation and short-channel effects.
Implementation Method 1
forming a mask line over the preliminary device structure, the mask line extending across the fin structure and the dummy structure; forming along the first side of the fin structure a source trench and a drain trench in the deposited layer, at opposite sides with respect to the mask line
Data Source
AI summary
A method is provided for forming a FET device. The method includes: forming a preliminary device structure comprising a fin structure comprising a layer stack comprising channel layers and non-channel layers alternating the channel layers, and a deposited layer along a first side of the fin structure and a dummy structure along a second side of the fin structure; forming a mask line; forming along a first side of the fin structure a source and drain trench in the deposited layer; forming a set of source and drain cavities in the layer stack, by etching the fin structure from the source trench and the drain trench; forming a source body and a drain body comprising a respective common body portion a set of prongs protruding from the respective common body portion into the source and drain cavities; embedding the mask line in a cover material and removing the mask structure; forming a gate trench by etching the dummy structure; forming a set of gate cavities in the layer stack by etching the fin structure from the gate trench; and forming a gate body comprising a common gate body portion in the gate trench and a set of gate prongs protruding from the common gate body portion into the gate cavities.