Field-Effect Transistor Electrode Layout for Optical Defect Inspection
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Solution Overview
Problem
Existing methods for manufacturing field-effect transistors (FETs) struggle to distinguish between defective formation of source/drain electrodes and wires during inspection, as the appearance of both under the same exposure and development conditions makes them indistinguishable.
Innovation Solution
The FET design incorporates source and drain electrodes with a continuous phase containing an electrically conductive and organic component, where the connecting portions with wires also form a continuous phase, differing in optical reflectance and surface roughness, allowing for easy differentiation during inspection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If back surface exposure is performed using a gate electrode as a light shielding mask to form source/drain electrodes, then positional accuracy of source/drain electrodes is improved, but it becomes impossible to distinguish defective formation of source/drain electrodes from defective formation of wires in the inspection step
Solution Approach 1:
The patent applies local quality by forming source/drain electrodes and wires using different exposure methods (back surface exposure vs. front surface exposure), creating locally distinct optical properties. The source/drain electrodes formed by back surface exposure have different reflectance characteristics compared to wires formed by front surface exposure, enabling local differentiation during inspection while maintaining high positional accuracy for both structures
Solution Approach 2:
The patent utilizes color changes (optical reflectance differences) to enable inspection differentiation. By controlling the exposure conditions and forming structures with different optical properties, the source/drain electrodes and wires exhibit distinguishable reflectance characteristics under optical microscopy, allowing defective formation to be identified without confusion
2Ease of manufacture
If a mask is used to collectively form source/drain electrodes and wires, then alignment of the mask is required, increasing process complexity
Solution Approach 1:
The patent segments the formation process into two distinct exposure steps: back surface exposure for source/drain electrodes and front surface exposure for wires. This segmentation eliminates the need for mask alignment between electrodes and wires, as each structure is formed independently without requiring relative positioning, thereby reducing process complexity while maintaining ease of manufacture
Solution Approach 2:
The patent uses the gate electrode itself as a light shielding mask during back surface exposure, inverting the conventional approach of using a separate photomask. This inversion eliminates the need for external mask alignment, as the gate electrode's position defines the source/drain electrode positions automatically, simplifying the manufacturing process
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the manufacturing of FETs that can be easily inspected for defects, facilitating accurate identification of electrode and wire formations and improving the accuracy of defect detection.
Implementation Method 1
an electrically conductive film is formed by applying an electrically conductive paste containing electrically conductive particles and a photosensitive organic component
Data Source
Figure 1~2
Figure 3A~3A(d)
Figure 3B~3B(g)
AI summary
An object is to provide a field-effect transistor that can be manufactured at low cost using a simple process and that makes it easy to distinguish a wire from source/drain electrodes during inspection, the field-effect transistor comprising, on a substrate, a source electrode, a drain electrode, and a gate electrode; a semiconductor layer in contact with the source electrode and the drain electrode; wires individually electrically connected to the source electrode and the drain electrode; and a gate insulating layer that insulates the semiconductor layer from the gate electrode, wherein a connecting portion between the source electrode and the wire forms a continuous phase, and a connecting portion between the drain electrode and the wire forms a continuous phase, the portions constituting the continuous phases contain at least an electrically conductive component and an organic component, and integrated values of optical reflectance at a region of a wavelength of 600 nm or more and 900 nm or less on the wires are higher than integrated values of optical reflectance at a region of a wavelength of 600 nm or more and 900 nm or less on the source electrode and the drain electrode.