FET Overcurrent Detection Circuit with Dual Polarity Sensing
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Solution Overview
Problem
Conventional overcurrent detectors in power FETs, particularly in class D power amplifiers, face challenges in detecting overcurrents quickly due to cyclic speed limitations and inability to handle negative voltage states, leading to potential damage and increased costs in noisy environments.
Innovation Solution
An overcurrent detector that measures currents through FETs in both positive and negative directions, allowing for detection of all four voltage states in a switching half bridge, which reduces response time requirements and eliminates overcurrent detection holes, using circuitry that converts negative Vds to positive Vds for unified sensing and incorporates spike suppression to enhance performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional overcurrent detectors are used, then cost and complexity are reduced, but response time is too slow (100-200 ns) to detect overcurrent events between detection intervals
Solution Approach 1:
The patent segments the overcurrent detection function into two independent parallel paths: one for detecting overcurrent during the high-side FET on-time using Vds voltage, and another for detecting overcurrent during the low-side FET on-time using Vs voltage. This segmentation allows each detection path to operate independently with optimized response times, eliminating the detection holes that occur in sequential detection schemes.
2Adaptability or versatility
If conventional single-direction current detection is used, then circuit complexity is reduced, but detection coverage is limited to only half of the possible voltage measurement situations
Solution Approach 1:
The patent implements a unified detection architecture where the same comparator and reference voltage circuitry are used to detect overcurrent in both high-side and low-side FETs. The system universally monitors both Vds and Vs voltages, enabling the single detection circuit to handle all four possible voltage states (positive/negative Vds and Vs combinations) rather than requiring separate detection circuits for each direction.
3Loss of time
If integrated overcurrent detection and gate drive control is provided, then response time is reduced to under 46 ns, but the circuit becomes more complicated and costly
Solution Approach 1:
The patent merges the overcurrent detection function with the existing gate drive control circuitry by sharing common components such as the comparator, reference voltage sources, and logic gates. The detection circuit integrates directly into the gate drive IC, allowing the same control logic that manages FET switching to also monitor overcurrent conditions and trigger protective shutdown, thereby achieving fast response without proportionally increasing complexity.
4Reliability
If fast response overcurrent detection is implemented, then overcurrent detection holes are eliminated, but noise susceptibility increases in environments with reverse recovery events
Solution Approach 1:
The patent introduces blanking circuits as intermediary elements that temporarily disable the overcurrent detection function during known noisy periods, specifically during reverse recovery events. The blanking circuit monitors the switching state and suppresses detection during intervals when voltage spikes and noise are expected, preventing false overcurrent triggers while maintaining detection sensitivity during normal operation intervals.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables faster and more robust overcurrent detection, reducing the risk of damage and cost by eliminating overcurrent detection holes and creeping current issues, while maintaining adequate protection without increasing complexity or cost.
Implementation Method 1
current detection for a FET can be achieved by measuring a voltage drop across the FET output, or the drain-source node. When the FET is conducting, and current flows from the drain to the source, the measured voltage drop is proportional to the current.
Implementation Method 2
circuitry that converts negative Vds to positive Vds for unified sensing
Implementation Method 3
incorporates spike suppression to enhance performance
Data Source
AI summary
A circuit and method for determining overcurrent in a FET detects an output voltage of the FET in both a positive and negative polarity. The related positive or negative currents through the FET can be measured to determine whether an overcurrent condition exists. By measuring positive and negative currents in the FET, the overcurrent detector can obtain twice as much information as when measuring a positive current alone, and can respond more readily to overcurrent conditions. The overcurrent detector avoids the constraints typically observed in cycle-by-cycle PWM control with single polarity Vds sensing, while permitting a relaxation in the timing requirements for current sensing. A spike suppression circuit also contributes to longer sensing intervals.