FET Contact Layout With Overlapping Landing Regions for Low GIDL
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Solution Overview
Problem
Field-Effect transistor (FET) devices in semiconductor integrated circuits experience high leakage current due to Gate Induced Drain Leakage (GIDL), especially under high drain-gate bias, which is exacerbated by increasing pixel density, leading to power consumption issues and reduced process yield.
Innovation Solution
A semiconductor device design where the gate landing region overlaps with the source and drain landing regions, allowing for a reduced gate width without altering the channel doping region or gate width, thus minimizing device size without increasing leakage current or affecting alignment accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If the distance between the gate and the drain terminal is increased to reduce GIDL, then the leakage current is reduced, but the width of the pixel unit is increased, thereby reducing the pixel density
Solution Approach 1:
The patent repositions the gate landing region from a lateral arrangement to a vertical stacking arrangement, allowing it to overlap with the source and drain landing regions in the vertical dimension. This dimensional change enables the gate to be electrically connected while occupying less lateral space, thus reducing pixel unit width without compromising GIDL reduction
Solution Approach 2:
The gate landing region is nested within or overlapping the source and drain landing regions in the vertical stacking structure. This nesting allows multiple functional regions to occupy the same lateral footprint by utilizing the vertical dimension, thereby reducing the overall pixel unit width while maintaining electrical connectivity
2Area of stationary object
If the gate width is reduced to minimize device size, then the pixel density is increased, but the alignment of the gate contact structure is adversely affected, thereby reducing the process yield
Solution Approach 1:
By moving the gate landing region connection to the vertical dimension through stacking, the lateral gate width can be reduced without compromising alignment. The vertical stacking provides additional spatial freedom that decouples the gate width from the alignment constraints, allowing smaller device sizes while maintaining manufacturing precision
Solution Approach 2:
The vertical stacking structure acts as an intermediary that mediates between the reduced gate width and the alignment requirements. The stacked configuration allows the gate landing region to be electrically connected through the vertical dimension, serving as a bridge that enables both small device size and adequate alignment tolerance
3Productivity
If the gate width is substantially smaller than the channel length to reduce device size, then the pixel density is increased, but the alignment of the gate contact structure is adversely affected
Solution Approach 1:
The vertical stacking arrangement allows the gate landing region to connect to the gate electrode through the vertical dimension rather than requiring extensive lateral overlap. This enables the gate width to be reduced below the channel length while maintaining proper alignment, thereby increasing pixel density without sacrificing ease of operation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design effectively reduces the overall size of the semiconductor device while maintaining low leakage current and alignment precision, addressing the challenges of high GIDL and pixel density.
Implementation Method 1
Field-Effect transistor (FET) devices in a semiconductor integrated circuit may generate high leakage current when the source and drain are in the off state (I-off), due to the band-to-band tunneling effect between the drain and gate insulators
Data Source
AI summary
A semiconductor device includes: a substrate, a gate structure, a source region, a drain region, a gate contact structure, a source contact structure and a drain contact structure. The gate structure, source region and drain region are all disposed in the substrate. The gate contact structure lands on a gate landing region over the gate structure and electrically contacts with the gate structure. The source contact structure lands on a source landing region over the source region and electrically contacts with the source region. The drain contact structure lands on a drain landing region over the drain region and electrically contacts with the drain region. Wherein, at least one of the source landing region and the drain landing region at least partially overlaps with the gate landing region in an arranging direction of the source region and the drain region.