FET Passivation Layers for Dangling-Bond Drive Current Loss
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The scaling down of semiconductor devices increases complexity and reduces the drive current due to surface defects in the active regions, such as dangling bonds, which trap charge carriers and hinder performance.
Innovation Solution
The application of passivation layers comprising fluorine, nitrogen, hydrogen, and/or chlorine atoms on the active regions of FETs to react with dangling bonds, reducing or eliminating surface defects and enhancing the drive current by 20% to 50%.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If semiconductor devices are scaled down to increase storage capacity and processing speed, then device density and performance are improved, but surface defects such as dangling bonds increase, trapping charge carriers and reducing drive current
Solution Approach 1:
The patent applies passivation layers containing fluorine, nitrogen, hydrogen, and/or chlorine atoms that chemically react with harmful dangling bonds on the semiconductor surface, converting these defects into beneficial passivated states. This chemical reaction eliminates the harmful effect of dangling bonds that trap charge carriers, thereby restoring and enhancing drive current while maintaining the benefits of device scaling.
Solution Approach 2:
The patent changes the chemical composition parameters of the semiconductor surface by introducing passivation atoms (fluorine, nitrogen, hydrogen, chlorine) that alter the surface chemistry. This parameter change transforms the surface from a defective state with dangling bonds to a passivated state, improving charge carrier mobility and drive current without requiring changes to the device geometry or scaling dimensions.
2Speed
If device dimensions are reduced to meet higher performance demands, then processing speed and storage capacity increase, but manufacturing complexity increases
Solution Approach 1:
The patent applies passivation layers at a preliminary stage in the manufacturing process, before subsequent processing steps. By passivating the surface early, the patent prevents defect formation and eliminates the need for complex defect remediation steps later in the process, thereby simplifying the overall manufacturing complexity while enabling high-performance scaled devices.
3Reliability
If passivation layers are applied to react with dangling bonds, then drive current increases by 20% to 50%, but additional manufacturing steps are required
Solution Approach 1:
The patent merges the passivation step with existing manufacturing processes by applying passivation layers using standard deposition techniques that can be integrated into the existing fabrication flow. The passivation process is combined with other surface treatment or deposition steps, reducing the number of separate process steps while achieving the 20% to 50% drive current improvement through effective dangling bond passivation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The passivation layers improve the surface quality of FETs by mitigating vacancies, thereby increasing the drive current and enhancing device performance.
Implementation Method 1
The application of passivation layers comprising fluorine, nitrogen, hydrogen, and/or chlorine atoms on the active regions of FETs to react with dangling bonds
Implementation Method 2
The passivation layers improve the surface quality of FETs by mitigating vacancies
Data Source
AI summary
The structure of a semiconductor device with passivation layers on active regions of FET devices and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes a substrate, first and second source/drain (S/D) regions disposed on the substrate, nanostructured channel regions disposed between the first and second S/D regions, a passivation layer, and a nanosheet (NS) structure wrapped around the nanostructured channel regions. Each of the S/D regions have a stack of first and second semiconductor layers arranged in an alternating configuration and an epitaxial region disposed on the stack of first and second semiconductor layers. A first portion of the passivation layer is disposed between the epitaxial region and the stack of first and second semiconductor layers and a second portion of the passivation layer is disposed on sidewalls of the nanostructured channel regions.