FET Phase Alignment via Substrate Metal Layers
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Solution Overview
Problem
High-frequency field-effect transistors face performance deterioration due to phase mismatches among fingers caused by uneven electrical lengths, leading to reduced output power and efficiency, especially when using substrates with high thermal conductivity like silicon carbide or gallium nitride, where simple slow-wave transmission line structures fail to equalize electrical lengths effectively.
Innovation Solution
A field-effect transistor design with semiconductor substrate, drain, source, and gate electrodes, where metal layers are strategically placed beneath the substrate to adjust electrical lengths by varying their number and distance from drain electrodes, ensuring phase alignment through increased capacitance and delayed signal propagation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If matching circuits are added to each finger to equalize electrical lengths, then phase alignment is improved, but device size significantly increases
Solution Approach 1:
Metal layers are introduced as intermediary elements beneath the substrate to adjust electrical lengths. These metal layers act as capacitive mediators that equalize the electrical paths from input to output terminals across different fingers without requiring additional matching circuits, thereby achieving phase alignment while avoiding increased device size
Solution Approach 2:
The solution moves from adjusting electrical lengths in the planar dimension (by adding matching circuits) to adjusting them in the vertical dimension (by adding metal layers beneath the substrate). This dimensional shift allows for electrical length equalization through capacitance control rather than through-circuit adjustments
2Reliability
If the electrical length of each finger is increased to equalize phases, then phase alignment is improved, but potential difference increases and characteristics degrade
Solution Approach 1:
Instead of changing the electrical length parameter by adding physical path length, the invention changes the capacitance parameter by introducing metal layers. This allows for electrical length equalization through capacitance adjustment rather than through increasing physical length, thereby avoiding increased potential difference and its harmful effects
3Reliability
If metal layers are made closer to drain and gate electrodes to adjust electrical length, then phase alignment is improved, but parasitic capacitance increases and characteristics degrade
Solution Approach 1:
Metal layers are strategically positioned beneath specific regions (such as under the substrate or under source/drain regions) rather than uniformly close to all electrodes. This localized placement allows for electrical length adjustment in specific areas while minimizing the generation of unwanted parasitic capacitance in other critical regions
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances the efficiency and output power of high-frequency field-effect transistors by equalizing signal phases across fingers, minimizing parasitic capacitance, and maintaining heat dissipation efficiency, even with high thermal conductivity substrates.
Implementation Method 1
the electrical length of each finger is changed due to a metal layer just below the electrode
Data Source
AI summary
A field effect transistor according to the present invention includes a semiconductor substrate, a plurality of drain electrodes provided on a first surface of the semiconductor substrate and extending in a first direction, an input terminal, an output terminal, and a plurality of metal layers provided in the semiconductor substrate apart from the first surface and extending in a second direction crossing the first direction, in which the plurality of metal layers include a first metal layer and a second metal layer which is longer than the first metal layer and which crosses more drain electrodes than the first metal layer when seen from a direction perpendicular to the first surface, and among the plurality of drain electrodes, those having a smaller length of line from the input terminal to the output terminal are provided with more metal layers directly thereunder.