Semiconductor FET Layout With Opposed Prongs for CPP Scaling
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Solution Overview
Problem
Current integrated circuit design faces challenges in scaling contacted poly pitch (CPP) and achieving low track height due to limitations in gate length, source/drain contact area, and gate spacer width, which restricts area efficiency and circuit cell width.
Innovation Solution
The semiconductor device structure incorporates a unique design with laterally offset source/drain and gate structures, allowing for reduced or omitted dielectric spacers and shared S/D bodies, enabling a compact footprint and efficient CPP scaling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional FET structures with gate spacers are used, then device functionality is maintained, but CPP scaling is limited and track height increases
Solution Approach 1:
The patent removes the gate spacer component entirely from the FET structure. By directly contacting the gate electrode to the source/drain regions without an intervening spacer layer, the design eliminates the spacer thickness constraint that traditionally limited CPP scaling, thereby enabling smaller pitch dimensions
Solution Approach 2:
The gate electrode and source/drain contact structures are merged or directly joined without the traditional spacer separation. This integration allows the gate to extend directly to the source/drain regions, reducing the overall cell width and enabling tighter packing of adjacent transistors
2Area of stationary object
If gate spacers are included in FET design, then electrical isolation is ensured, but cell width and track height increase
Solution Approach 1:
The gate spacer is extracted/removed from the structure. Electrical isolation is maintained through alternative means such as the inherent properties of the gate electrode material or direct contact geometry that prevents unwanted electrical interaction while minimizing space occupation
Solution Approach 2:
The patent transitions from a planar isolation approach to a vertical or three-dimensional arrangement where the gate electrode contacts source/drain regions in a manner that provides electrical isolation through spatial positioning in multiple dimensions rather than relying on lateral spacer separation
3Adaptability or versatility
If more routing tracks are allocated per circuit cell, then routing capacity increases, but cell height increases
Solution Approach 1:
The patent enables routing capacity expansion without increasing cell height by utilizing horizontal space more efficiently. The reduced CPP and compact FET footprint create additional horizontal routing capacity within the same vertical envelope, effectively adding routing tracks in the lateral dimension rather than stacking tracks vertically
4Productivity
If gate length is reduced for scaling, then transistor density increases, but source/drain contact area and gate spacer width become limiting factors
Solution Approach 1:
By removing the gate spacer, the patent eliminates the spacer width constraint that previously co-limited scaling with gate length. This allows gate length and source/drain contact dimensions to be scaled independently, enabling continued transistor density improvement without being bottlenecked by spacer fabrication precision
Solution Approach 2:
The patent segments the scaling process by allowing independent optimization of gate length, source/drain contact area, and gate electrode dimensions. Without the spacer coupling these features, each dimension can be scaled and manufactured with appropriate precision requirements tailored to its specific function rather than being constrained by the most restrictive spacer dimension
Data Source
AI summary
The disclosure relates to a semiconductor device structure. The device structure comprises a first and second FETs, each comprising respective S/D structures, a respective channel structure and a respective gate structure. Each S/D structure comprises an S/D body and a set of vertically spaced apart S/D prongs protruding laterally from the S/D body. The S/D prongs of the first and second FETs extend in opposite lateral directions. Each gate structure comprises a gate body and a set of gate prongs protruding laterally from the gate body into spaces between channel layers of the respective channel structures. The gate prongs of the first and second FETs extend in opposite lateral directions.