Gate-All-Around FET Protection Structures for Lower Parasitic Capacitance
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Solution Overview
Problem
The miniaturization of field effect transistors (FETs) leads to increased parasitic capacitances, which limit their operation speed, especially at high frequencies, due to unwanted capacitive coupling between the gate electrode and source/drain structures.
Innovation Solution
The implementation of protection structures, formed from semiconductor materials, is used to separate the gate electrode from the trench isolation structure and source/drain structures, preventing further recessing of the trench isolation and reducing parasitic capacitance by maintaining the gate electrode above a certain surface level, thereby enhancing the operational performance of the semiconductor device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If FETs are miniaturized to increase integration density, then circuit functionality and compactness are improved, but parasitic capacitances increase which limits operation speed
Solution Approach 1:
The patent introduces an intermediate structure (dummy gate or protection structure) positioned between the gate electrode and the trench isolation structure. This intermediary prevents direct contact and reduces parasitic capacitance coupling, thereby maintaining high operation speed despite device miniaturization.
Solution Approach 2:
The patent extends the gate structure vertically by adding bottom portions that protrude below the trench isolation structure surface. This dimensional extension creates spatial separation in the vertical dimension, reducing parasitic capacitance while maintaining the compact lateral footprint of the device.
2Reliability
If gate electrode is allowed to extend deeper to improve control, then transistor performance is improved, but unwanted capacitive coupling with source/drain structures increases
Solution Approach 1:
The dummy gate structure serves as a mediator that allows the gate electrode to extend deeper for improved control while preventing direct capacitive coupling with source/drain structures. The intermediary maintains electrical isolation while enabling performance enhancement.
Solution Approach 2:
The gate structure is segmented into multiple portions: the main gate electrode and separate bottom portions that extend below the trench isolation structure. This segmentation allows the bottom portions to provide control enhancement while being spatially separated from source/drain structures, reducing parasitic capacitance.
3Device complexity
If trench isolation structure is recessed to accommodate gate structure, then device integration is improved, but gate electrode may contact source/drain structures increasing parasitic capacitance
Solution Approach 1:
The patent performs preliminary action by forming dummy gates or protection structures before final gate electrode formation. These preliminary structures prevent excessive recessing of the trench isolation structure and guide the gate electrode positioning to avoid contact with source/drain structures, thereby preventing parasitic capacitance formation.
Solution Approach 2:
The solution addresses the integration challenge by utilizing the vertical dimension. Bottom portions of the gate structure extend below the trench isolation structure surface, achieving deep integration control while maintaining lateral separation from source/drain structures, thus avoiding capacitive coupling.
Data Source
AI summary
A semiconductor device, a semiconductor chip and manufacturing methods thereof are provided. The semiconductor device includes: channel structures, vertically spaced apart from one another; a gate structure, intersecting the channel structures and wrapping around each of the channel structures; source/drain structures, in lateral contact with the channel structures from opposite sides of the channel structures; and protection structures, separately disposed along a bottom surface of the gate structure, wherein the channel structures are located between the protection structures, and the protection structures comprise a semiconductor material.