FET Gate Dielectric PUF Using Random High-k Threshold Variation
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Solution Overview
Problem
Semiconductor devices face challenges in obtaining a stable physically unclonable function (PUF) output due to sensitivity to environmental conditions, requiring additional stabilization and error-correction techniques, which complicates secure chip identification and authentication.
Innovation Solution
A semiconductor structure and method that utilize random threshold voltage variation in field effect transistors (FETs) by randomly nucleating high-k materials in gate regions, creating unique threshold voltages across multiple gate regions, which serve as a physically unclonable function for secure chip identification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional PUF structures are used, then unique identification is provided, but the output is sensitive to environmental conditions requiring additional stabilization techniques
Solution Approach 1:
The patent changes the physical parameter of the gate dielectric layer by embedding high-k material with different dielectric constants at different locations. This creates location-dependent threshold voltage variations that are inherently stable and less sensitive to environmental conditions, eliminating the need for complex stabilization techniques while maintaining unique identification capability
Solution Approach 2:
The patent applies local quality by embedding high-k material at specific locations within the gate dielectric layer (first location vs second location). Each location has different dielectric properties, creating locally distinct threshold voltage characteristics that serve as stable, unique identifiers without requiring additional stabilization circuits
2Reliability
If high-k material is embedded in gate dielectric layer, then random threshold voltage variation is achieved for PUF, but manufacturing process complexity increases
Solution Approach 1:
The patent performs preliminary action by embedding the high-k material during the gate dielectric layer formation process itself, rather than as a separate subsequent step. The high-k material is incorporated into the gate dielectric layer before transistor fabrication is complete, allowing the PUF characteristics to be established early in the manufacturing process
Solution Approach 2:
The patent merges the PUF structure creation with the standard gate dielectric layer formation process. By combining these two functions into a single integrated process step, the patent achieves random threshold voltage variation without adding separate manufacturing complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The random threshold voltage variation provides a stable and unique digital fingerprint for each semiconductor device, enhancing security and authenticity verification without the need for extensive stabilization and error-correction techniques.
Implementation Method 1
randomly nucleating a high-k material in the one or more gate regions
Data Source
AI summary
A semiconductor structure may include one or more metal gates, one or more channels below the one or more metal gates, a gate dielectric layer separating the one or more metal gates from the one or more channels, and a high-k material embedded in the gate dielectric layer. Both the high-k material and the gate dielectric layer may be in direct contact with the one or more channels. The high-k material may provide threshold voltage variation in the one or more metal gates. The high-k material is a first high-k material or a second high-k material. The semiconductor structure may only include the first high-k material embedded in the gate dielectric layer. The semiconductor structure may only include the second high-k material embedded in the gate dielectric layer. The semiconductor structure may include both the first high-k material and the second high-k material embedded in the gate dielectric layer.