FET Gate with Recessed Work Function Metal and Dielectric Cap

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Solution Overview

Problem

Conventional techniques for forming field effect transistors (FETs) risk shorts between the replacement metal gate and adjacent source/drain contacts due to the structure of middle of the line (MOL) contacts in integrated circuit (IC) structures.

Innovation Solution

A field effect transistor (FET) with a replacement metal gate configuration that includes a conformal gate dielectric layer, a stack of gate conductor layers with a recessed work function metal layer, and a conductive fill material layer, along with a dielectric gate cap to minimize the occurrence of shorts by narrowing the width of the gate conductor stack near the gate cap and protecting the outer sidewall and top surface of the conductive fill material layer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional techniques are used to form FETs with MOL contacts, then the manufacturing process is simple, but shorts occur between source/drain contacts and the gate

Engineering Contradiction:
Improveshort preventionVSAvoidgate structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The gate conductor stack is segmented into multiple layers with different functions: the work function metal layer is recessed relative to the conductive fill material layer, creating distinct functional zones. This segmentation allows the gate structure to simultaneously provide electrical connectivity while maintaining physical separation from source/drain contacts, thus preventing shorts without overly complicating the overall device architecture.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The gate structure implements local quality by having the work function metal layer recessed at specific locations (adjacent to source/drain contacts) while maintaining full coverage elsewhere. This localized modification provides short prevention exactly where needed without affecting the gate's overall functionality or requiring complete restructuring of the entire gate system.

Inventive Principle:
Principle #3Local quality

2Reliability

If the gate conductor stack width is maintained uniformly, then manufacturing is easier, but shorts occur between gate and source/drain contacts

Engineering Contradiction:
Improveshort preventionVSAvoidgate conductor layer alignment
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The work function metal layer is deposited and recessed before the conductive fill material layer is completed. This preliminary action of creating the recessed work function layer establishes the short-prevention geometry in advance, guiding subsequent manufacturing steps and ensuring proper alignment without requiring complex real-time adjustments during fill material deposition.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The recessed work function metal layer acts as an intermediary structure between the conductive fill material layer and the source/drain contacts. This intermediate recessed portion provides a buffer zone that physically separates the conductive elements, preventing direct contact and shorts while simplifying the alignment requirements for the overall gate structure fabrication.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS10217839B2Field effect transistor (FET) with a gate having a recessed work function metal layer and method of forming the FET
Publication Date: 2019.02.26 GLOBALFOUNDRIES US INC
  • US10217839B2 patent drawing
  • US10217839B2 patent drawing
  • US10217839B2 patent drawing

AI summary

Disclosed is a field effect transistor (FET) with a replacement metal gate (RMG) and a method of forming the FET. The RMG includes a conformal gate dielectric layer and a stack of gate conductor layers on the gate dielectric layer. The stack includes a conformal work function metal (WFM) layer and a conductive fill material (CFM) layer on the WFM layer. Within the stack, the top surface of the CFM layer is above the level of the top of an adjacent vertical portion of the WFM layer. A dielectric gate cap has a center portion and an edge portion. The center portion is above the top surface of the CFM layer and the edge portion is above the top of the adjacent vertical portion of the WFM layer and is further positioned laterally immediately adjacent to an upper portion of an outer sidewall of the CFM layer.