FET RF Switch Off-State Linearization Region
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
FET-based RF switches suffer from harmonic distortion due to non-linear capacitance when in the off-state, leading to interference with receiver circuitry, and traditional off-state linearization networks introduce extra parasitic capacitance that reduces the figure of merit performance and occupies valuable circuit space.
Innovation Solution
The design incorporates an off-state linearization region within each FET cell, featuring a doped well and dielectric layer with conductive stripes that provide a second non-linear capacitance, which combines with the inherent finger region capacitance to form a substantially linear total off-state capacitance, reducing harmonic distortion without the need for external linearization networks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If an off-state linearization network is placed in parallel with the RF switch to reduce harmonic distortion, then the harmonic distortion is reduced, but extra parasitic capacitance is introduced that reduces figure of merit performance
Solution Approach 1:
The off-state linearization network is merged with the FET cell structure by integrating it into the same semiconductor substrate. The linearization network shares physical space with the FET components through共用 substrate area, eliminating the need for separate external linearization networks while maintaining harmonic distortion reduction functionality.
Solution Approach 2:
The off-state linearization network is nested within the FET cell structure. The linearization network components (capacitors, resistors) are positioned within the same bounding box as the FET, utilizing the space between and around the FET fingers. This nesting approach allows the linearization function to be contained within the FET cell footprint without adding external components.
2Object-generated harmful factors
If an off-state linearization network is placed in parallel with the RF switch to reduce harmonic distortion, then the harmonic distortion is reduced, but valuable circuit real estate is occupied
Solution Approach 1:
The off-state linearization network is merged with the FET cell structure by integrating it into the same semiconductor substrate. The linearization network shares physical space with the FET components, eliminating the need for separate external linearization networks while maintaining harmonic distortion reduction functionality.
Solution Approach 2:
The layout utilizes two-dimensional space optimization by arranging the linearization network components in the lateral plane around the FET fingers rather than extending the circuit footprint. Capacitors are positioned in the spaces between parallel fingers, and resistors are routed along the periphery, effectively using available white space within the cell boundary.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces undesirable harmonic distortion and preserves the figure of merit performance of RF switches while minimizing circuit size, eliminating the need for external linearization networks and maintaining performance.
Implementation Method 1
the finger region has a first non-linear off-state capacitance that increases as drain-to-source voltage increases within a first voltage range
Implementation Method 2
undesirable harmonics are generated from the transmit signals in part due to non-linear capacitance inherent to the RF switch
Data Source
AI summary
An electronic component made up of field-effect transistor (FET) cells is disclosed. Each FET cell includes a finger region having drain, gate, and source fingers disposed over a semiconductor substrate. An isolation region extends across a first end of the finger region. An off-state linearization region abuts the first end of the isolation region. A doped well is disposed within the off-state linearization region over the semiconductor substrate. A dielectric layer is disposed over the doped region. A first conductive stripe is disposed over the dielectric layer in longitudinal alignment with the drain finger. A second conductive stripe is disposed over the dielectric layer in longitudinal alignment with the drain finger. A drain finger electrode is aligned over and coupled to both the drain finger and the first conductive stripe. A source finger electrode is aligned over and coupled to both the source finger and the second conductive stripe.