Self-Aligned Contact Formation in Field-Effect Transistors
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Solution Overview
Problem
Existing field-effect transistor structures face challenges in reducing the margin for shorting between the gate electrode and source/drain contacts, particularly in both long-channel and short-channel devices, due to limitations in dielectric material removal processes.
Innovation Solution
The proposed structure includes a gate electrode with sidewall spacers, source/drain regions, and contacts over the source/drain regions, with an interlayer dielectric layer that is patterned and partially removed using an etching process to create a self-aligned contact formation, ensuring proper exposure and isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If dielectric material is removed to expose source and drain for contact formation, then contact formation is enabled, but the margin for shorting between gate electrode and source/drain contacts is reduced
Solution Approach 1:
The patent applies preliminary action by forming a mandrel structure before contact formation that defines the contact opening location. The mandrel is positioned to ensure proper spacing from the gate electrode before dielectric removal, pre-establishing the correct geometry to prevent shorting while enabling contact formation.
Solution Approach 2:
The patent introduces a mandrel as an intermediary element that mediates between the gate electrode and the contact opening. This mandrel structure serves as a temporary placeholder that defines the contact location and maintains proper spacing, allowing contact formation without directly exposing the source/drain to the gate electrode.
2Manufacturing precision
If self-aligned etching is used to pattern interlayer dielectric, then manufacturing precision is improved, but the interlayer dielectric layer must be fully removed which reduces shorting margin
Solution Approach 1:
The patent applies partial action by selectively removing the interlayer dielectric layer only in specific regions where contacts are needed, rather than fully removing it across the entire structure. This partial removal approach maintains dielectric material in areas that would provide shorting protection while still enabling precise contact formation through self-aligned etching.
Solution Approach 2:
The patent applies local quality by creating different dielectric layer configurations in different regions of the structure. The interlayer dielectric is removed locally at contact sites while being preserved in other regions, providing localized contact formation with self-aligned precision while maintaining global shorting protection through retained dielectric material.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces the risk of shorting and improves the fabrication process by fully removing the interlayer dielectric layer in a self-aligned manner, enabling precise contact formation and enhancing the performance of both long-channel and short-channel field-effect transistors.
Implementation Method 1
The etching process removes dielectric material from locations over the semiconductor material constituting the source and drain
Data Source
AI summary
Structures for a field-effect transistor and methods of forming a field-effect transistor. A sidewall spacer is arranged adjacent to a sidewall of a gate electrode, a source/drain region is arranged laterally adjacent to the sidewall spacer, and a contact is arranged over the source/drain region and laterally adjacent to the sidewall spacer. The contact is coupled with the source/drain region. A section of an interlayer dielectric layer is laterally arranged between the contact and the sidewall spacer.