Self-Aligned Contact Formation in FET Circuits
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Solution Overview
Problem
As device features shrink, the thinner sidewall spacers in integrated circuits become vulnerable to physical and chemical effects during the plasma etch process, leading to unintended exposure of the gate and increased yield loss due to shorts and spacer thinning, which compromises device density and performance.
Innovation Solution
A combination fluoroether/hydrofluoroether-hydrofluorocarbon plasma etch is used to form self-aligned contacts without degrading the sidewall spacers, ensuring high selectivity and stopping on the semiconductor surface without an etch stop, thereby maintaining sidewall integrity and preventing spacer loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional HFC plasma etch is used to form self-aligned contacts, then contact formation is achieved, but sidewall spacers are degraded through physical shortening and chemical thinning
Solution Approach 1:
The patent modifies the plasma etch process parameters by switching from conventional HFC plasma to a fluorocarbon-based plasma etch process. This parameter change fundamentally alters the etching chemistry to be less aggressive toward silicon nitride sidewall spacers, preventing both physical sputtering and chemical thinning while maintaining effective oxide etching for contact formation.
2Productivity
If device features are shrunk to increase density, then chip density and performance are improved, but sidewall spacers become thinner and more vulnerable to etch damage
Solution Approach 1:
The patent addresses the vulnerability of thinner sidewall spacers by changing the plasma etch parameters to use fluorocarbon chemistry, which has lower sputtering yield and different chemical reactivity toward silicon nitride. This allows the etch process to selectively remove oxide without significantly impacting the already-thin sidewall spacers, maintaining gate protection even as device dimensions are reduced for higher density.
3Ease of manufacture
If sidewall spacers are thinned by etch effects, then contact etching becomes easier, but gate exposure and short risks increase
Solution Approach 1:
The patent changes the etch process parameters from HFC to fluorocarbon plasma, which provides sufficient etching power to remove oxide material for contact formation while being gentler on silicon nitride sidewall spacers. This parameter optimization achieves the desired oxide removal without causing the harmful sidewall thinning that would expose the gate to shorts.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of self-aligned contacts with minimal sidewall spacer loss, reducing yield loss and improving device density and performance by maintaining gate sidewall integrity and avoiding etch stop formation, thus simplifying chip fabrication and enhancing yield in high-density FET applications.
Implementation Method 1
A combination fluoroether/hydrofluoroether-hydrofluorocarbon plasma etch etches the source/drain contacts self-aligned
Implementation Method 2
The FE-HFC or HFE-HFC plasma etch provides a highly selective plasma etch for etching silicon oxide selective to silicon nitride
Data Source
AI summary
A method of forming field effect transistor (FET) circuits, and forming Integrated Circuit (IC) chips with the FET circuits. After forming gate sidewall spacers, filling with insulation and planarizing to the top of the sidewall spacers, self-aligned source/drain contacts are etched through the insulation and said gate dielectric layer to source/drain regions. A combination fluoroether/hydrofluoroether-hydrofluorocarbon (*FE-HFC) plasma etch etches the source/drain contacts self-aligned. The self-aligned contacts are filled with conductive material, and FETs are wired together into circuits, connecting to FETs through the self-aligned contacts.