FET Layout With Source Bus Bar for Thermal Isolation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Heat interference occurs between unit FET groups in semiconductor devices, affecting their operation and high-frequency characteristics.
Innovation Solution
The semiconductor device incorporates a source bus bar overlapping via holes in the substrate, with a metal layer of lower thermal conductivity than the substrate, and strategically arranged transistors to sandwich the source bus bar, allowing for enhanced heat separation and reduced source inductance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If unit FET groups are arranged closely to increase device integration, then device density and productivity are improved, but heat interference between FET groups increases
Solution Approach 1:
The patent introduces a substrate with controlled thermal conductivity properties as an intermediary between adjacent FET groups. The substrate acts as a thermal management medium that allows heat dissipation while maintaining electrical isolation, thereby reducing heat interference between closely packed FET groups without compromising device integration density.
Solution Approach 2:
The patent applies different thermal conductivity characteristics to different regions of the substrate. By controlling the thermal conductivity of the substrate locally beneath or between FET groups, heat can be managed differently in different areas - with higher thermal conductivity regions for heat dissipation and lower thermal conductivity regions for thermal isolation between adjacent FET groups.
2Temperature
If via holes are filled with highly thermally conductive material to improve heat dissipation, then thermal management is improved, but source inductance increases
Solution Approach 1:
The patent optimizes the thermal conductivity parameter of the via hole filling material to achieve a balance between heat dissipation and inductance control. By carefully selecting and controlling the thermal conductivity parameter within an optimal range, the patent achieves sufficient heat dissipation while maintaining acceptable source inductance levels, resolving the trade-off between these two competing requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively suppresses thermal interference between FET groups, aligns signal phases, and improves high-frequency characteristics by reducing heat propagation and source inductance.
Implementation Method 1
a first via hole penetrating through the substrate as viewed from a thickness direction of the substrate
Implementation Method 2
a metal layer filled in the first via hole and having a thermal conductivity lower than a thermal conductivity of the substrate
Data Source
Figure 1
Figure 2
Figure 3
AI summary
A semiconductor device includes a source bus bar provided on a first surface of a substrate and overlapping with a first via hole penetrating through the substrate, a plurality of first transistors arranged in a second direction intersecting a first direction, each of the first transistors including a first source finger, a first drain finger and a first gate finger which extend in the first direction on the first surface, the first source finger being electrically connected to the source bus bar, and a plurality of second transistors arranged in the second direction, each of the second transistors including a second source finger, a second drain finger and a second gate finger which extend in the first direction on the first surface, the second source finger being electrically connected to the source bus bar, the first transistors and the second transistors sandwiching the source bus bar.