FET Source Region Chalcogen Doping for Latch-Up Robustness
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Solution Overview
Problem
Semiconductor devices, such as field effect transistors, face challenges with latch-up, over-current, and cosmic radiation robustness due to issues related to dopant spreading and contact resistance.
Innovation Solution
Incorporating chalcogen atoms, silicon atoms, and argon atoms into the source region of a field effect transistor structure after forming an oxide layer, which reduces deep diffusion into the semiconductor substrate and enhances latch-up robustness by forming a surface region with high atom concentration, thereby improving blocking capabilities and reducing contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If source region doping is reduced to improve latch-up robustness, then latch-up robustness is improved, but contact resistance increases
Solution Approach 1:
The patent applies local quality by creating a surface region with high chalcogen atom concentration specifically in the source region, while keeping the bulk source doping reduced. This localized modification at the surface improves latch-up robustness without compromising the bulk electrical properties needed for low contact resistance.
Solution Approach 2:
The patent changes the chemical composition parameter by incorporating chalcogen atoms (sulfur, selenium, or tellurium) into the source region surface. This compositional change modifies the electrical properties locally, enabling improved latch-up robustness through the high atom concentration surface region while maintaining acceptable contact resistance.
2Object-affected harmful factors
If dopant concentration is increased to reduce contact resistance, then contact resistance is reduced, but dopant spreading increases
Solution Approach 1:
The patent concentrates chalcogen atoms in a surface region with thickness of 1 nm to 1 μm, creating a localized zone that provides the necessary electrical properties without requiring high bulk dopant concentrations. This prevents dopant spreading into adjacent regions while maintaining low contact resistance at the contact interface.
Solution Approach 2:
The patent creates a composite structure in the source region combining silicon with chalcogen atoms (forming silicon-chalcogen compounds or complexes). This composite material provides both low contact resistance and resistance to dopant spreading, as the chalcogen atoms stabilize the local structure and prevent excessive diffusion.
3Manufacturing precision
If high temperature processing is used to form oxide layer, then oxide layer quality is improved, but dopant diffusion into substrate increases
Solution Approach 1:
The patent performs chalcogen atom incorporation into the source region before forming the oxide layer at high temperature. This preliminary action ensures that the chalcogen atoms are already in place to prevent dopant diffusion during the subsequent high-temperature oxide formation process, while the oxide layer quality is still improved by the high temperature processing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method improves latch-up robustness and blocking capabilities by preventing deep diffusion of dopants, maintaining low contact resistance even at reduced source doping, and enhancing cosmic radiation resistance in semiconductor devices.
Implementation Method 1
incorporating atoms of at least one atom type of a group of atom types into at least a part of the source region of the field effect transistor structure after forming the oxide layer
Data Source
AI summary
Some embodiments relate to a semiconductor device that includes a body region of a field effect transistor structure formed in a semiconductor substrate between a drift region of the field effect transistor structure and a source region of the field effect transistor structure. The semiconductor substrate includes chalcogen atoms at an atom concentration of less than 1×1013 cm−3 at a p-n junction between the body region and the drift region, and at least part of the source region includes chalcogen atoms at an atom concentration of greater than 1×1014 cm−3. Additional semiconductor device embodiments and corresponding methods of manufacture are described.