FET Source-Drain Contacts Extending Beyond Gate Spacer Height
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Solution Overview
Problem
As transistors miniaturize, higher parasitic contact resistance in the source-drain region leads to increased circuit delay due to smaller contact areas, which existing FET designs fail to effectively mitigate.
Innovation Solution
The method involves forming gate spacers over source and drain regions and epitaxially growing source and drain contacts that extend beyond the gate spacer height, ensuring physical and electrical contact while maintaining the same crystalline orientation as the substrate, thereby reducing parasitic contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If FET size is reduced for circuit miniaturization, then integration density is improved, but parasitic contact resistance increases due to smaller contact area
Solution Approach 1:
The source and drain contacts extend vertically beyond the gate spacer height, transitioning from a planar contact geometry to a three-dimensional structure. This vertical extension increases the contact area with the source and drain regions without increasing the lateral footprint, thereby reducing parasitic contact resistance while maintaining small device dimensions for high integration density
Solution Approach 2:
The gate spacers are formed first to define the contact region boundaries, and then the source and drain contacts are grown to extend beyond these boundaries. This preliminary positioning ensures that the contacts achieve sufficient overlap with the source and drain regions before finalization, optimizing the contact area and reducing parasitic resistance in advance
2Reliability
If contact area is increased to reduce parasitic contact resistance, then electrical performance is improved, but device area increases reducing integration density
Solution Approach 1:
The contact structures utilize the vertical dimension by extending beyond the gate spacer height, increasing contact area without proportionally increasing lateral device area. This three-dimensional contact geometry allows for reduced parasitic contact resistance while maintaining compact device footprints suitable for high-density integration
Solution Approach 2:
The source and drain contacts are specifically extended in the vertical region where electrical contact is needed, while the rest of the device maintains its miniaturized dimensions. This localized enhancement of contact area provides the necessary electrical performance without globally increasing device size, preserving integration density
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design results in significantly larger drain current in CMOS transistors, improving circuit performance by reducing parasitic contact resistance and enhancing operational efficiency.
Implementation Method 1
A growing step epitaxially grows a source contact and a drain contact
Data Source
AI summary
A field-effect transistor (FET) and methods for fabricating such. The FET includes a substrate having a crystalline orientation, a source region in the substrate, and a drain region in the substrate. Gate spacers are positioned over the source region and the drain region. The gate spacers include a gate spacer height. A source contact physically and electrically contacts the source region and extends beyond the gate spacer height. A drain contact physically and electrically contacts the drain region and extends beyond the gate spacer height. The source and drain contacts have the same crystalline orientation as the substrate.