Field Effect Transistor Source/Drain Isolation for Lower RF Capacitance
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Solution Overview
Problem
RF devices manufactured on bulk silicon substrates suffer from high source/drain junction capacitance, degraded linearity, harmonics, and noise, leading to increased costs due to the need for high resistivity silicon on insulator (SOI) wafers, which are expensive.
Innovation Solution
Incorporating shallow trench isolation structures within the source/drain regions of field effect transistors and using silicided semiconductor material over these structures to mimic SOI substrates, reducing source/drain junction capacitance and improving linearity without the high cost of SOI wafers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If RF devices are manufactured on bulk silicon substrates, then manufacturing cost is reduced, but source/drain junction capacitance increases and linearity degrades
Solution Approach 1:
The source/drain region is segmented into two parts: a first portion formed in the bulk silicon substrate and a second portion formed over shallow trench isolation structures. This segmentation allows the device to utilize both bulk silicon and SOI-like structures, achieving low capacitance and good linearity while maintaining cost-effectiveness through bulk substrate manufacturing.
Solution Approach 2:
Different regions of the source/drain structure are given different qualities: the first portion in the bulk substrate provides mechanical support and electrical connection, while the second portion over the shallow trench isolation structures provides low junction capacitance and improved linearity. This local differentiation resolves the contradiction between cost and performance.
2Reliability
If high resistivity silicon on insulator (SOI) wafers are used, then source/drain junction capacitance is reduced and linearity is improved, but manufacturing cost increases significantly
Solution Approach 1:
Instead of using expensive SOI wafers, the invention creates a localized SOI-like structure by forming shallow trench isolation structures within the bulk silicon substrate and depositing semiconductor material over them. This copying of the SOI configuration at specific locations provides the desired low capacitance and linearity performance without the high cost of full SOI wafers.
Solution Approach 2:
The invention replaces the expensive SOI wafer with a cheaper alternative: shallow trench isolation structures formed in bulk silicon. These isolated structures provide the necessary electrical isolation and low capacitance performance at a fraction of the cost of SOI wafers, making high-performance RF devices economically viable.
3Reliability
If shallow trench isolation structures are incorporated within source/drain regions, then source/drain junction capacitance is reduced, but device structure complexity increases
Solution Approach 1:
The invention merges the shallow trench isolation structure with the source/drain region formation process. The same isolation structures that provide electrical isolation between devices are also used to create the low-capacitance second portion of the source/drain region. This merging reduces overall device complexity while achieving the desired capacitance reduction.
Data Source
AI summary
The present disclosure relates to semiconductor structures and, more particularly, to field effect transistors and methods of manufacture. The structure includes: at least one gate structure having source/drain regions; at least one isolation structure within the source/drain regions in a substrate material; and semiconductor material on a surface of the at least one isolation structure in the source/drain regions.