High-Voltage FET Sidewall Spacer Layout for Surface Breakdown
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Solution Overview
Problem
High voltage field effect transistors suffer from surface breakdown voltage due to complex extended low doped drain configurations, leading to increased process complexity and cost.
Innovation Solution
The semiconductor structure incorporates field effect transistors with different sidewall spacer configurations, including a first gate spacer with laterally-straight outer sidewalls and a second gate spacer with a contoured portion and discrete openings, to improve reliability and reduce manufacturing complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If complex extended low doped drain configuration is used, then surface breakdown voltage is improved, but process complexity and manufacturing cost increase
Solution Approach 1:
The patent divides the gate spacer structure into two distinct types: first gate spacers with laterally-straight sidewalls and second gate spacers with contoured sidewalls featuring discrete openings. This segmentation allows different transistor regions to have optimized spacer configurations, improving surface breakdown voltage characteristics without requiring complex extended low doped drain structures throughout the entire device.
Solution Approach 2:
The invention applies different gate spacer configurations to different device regions based on local requirements. First gate spacers with straight sidewalls are used in regions requiring simple fabrication, while second gate spacers with contoured sidewalls and openings are used in regions needing enhanced breakdown voltage protection. This local differentiation resolves the contradiction by providing enhanced reliability only where necessary rather than universally.
2Reliability
If complex extended low doped drain configuration is used, then surface breakdown voltage is improved, but manufacturing cost increases
Solution Approach 1:
The patent segments the transistor population into two groups using different gate spacer configurations. The first gate spacers use simple laterally-straight sidewalls that are easier and cheaper to manufacture, while the second gate spacers with contoured sidewalls and openings provide enhanced breakdown protection. This segmentation reduces overall manufacturing cost compared to applying complex structures to all devices.
Solution Approach 2:
The invention changes the geometric parameters of the gate spacer sidewalls (from straight to contoured) and introduces discrete openings in specific regions. These parameter changes enable enhanced surface breakdown voltage characteristics in critical areas while maintaining simpler, lower-cost structures in non-critical areas, thus resolving the cost-reliability contradiction.
3Ease of manufacture
If first gate spacer with laterally-straight sidewalls is used, then manufacturing simplicity is improved, but surface breakdown protection is reduced
Solution Approach 1:
The patent applies first gate spacers with laterally-straight sidewalls in device regions where manufacturing simplicity is the priority and breakdown protection requirements are lower. Meanwhile, second gate spacers with contoured sidewalls and discrete openings are applied in regions requiring enhanced surface breakdown protection. This local quality differentiation resolves the contradiction by matching structure complexity to functional requirements.
4Reliability
If second gate spacer with contoured portion and discrete openings is used, then surface breakdown protection is improved, but manufacturing complexity increases
Solution Approach 1:
The patent segments the gate spacer implementation into two distinct designs: simple laterally-straight sidewalls for general applications and contoured sidewalls with discrete openings for enhanced protection. This segmentation allows the system to achieve improved surface breakdown protection in critical regions without requiring all devices to use the more complex contoured structure, thus balancing reliability improvement with acceptable manufacturing complexity.
Data Source
AI summary
A semiconductor structure includes a first field effect transistor including a first gate spacer having first laterally-straight bottom edges that coincide with top edges of first laterally-straight sidewalls of the first gate dielectric. The semiconductor structure further includes a second field effect transistor including a second gate dielectric that includes at least one discrete gate-dielectric opening that overlies a respective second active region, and a second gate spacer including a contoured portion that overlies and laterally surrounds a second gate electrode, and at least one horizontally-extending portion that overlies the second active region and including at least one discrete gate-spacer openings. The second field effect transistor may have a symmetric or non-symmetric configuration.