FET Layout Around STI Corners for Flicker Noise Reduction
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Solution Overview
Problem
Flicker noise and random telegraph noise (RTN) in field-effect transistors (FETs) are caused by defect states at the top cross-sectional corners of the semiconductor substrate, which have high mechanical stress and small radii of curvature, leading to charge carrier trapping and de-trapping, and are exacerbated by the gate electrode overlapping these corners.
Innovation Solution
The source/drain regions are spaced from the STI corners by using the gate electrode as a mask, and a silicide blocking structure is employed to prevent short circuits, while the gate is positioned within the inner perimeter of the isolation structure to avoid overlapping the STI corners, reducing charge carrier trapping at these defect states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the gate electrode overlaps the STI corners to improve device layout density, then manufacturing efficiency is improved, but flicker noise and RTN increase due to charge carrier trapping at defect states
Solution Approach 1:
The gate electrode is deliberately positioned to exclude the STI corner regions from its overlap area. By extracting the harmful STI corners from the gate's influence zone, the patent eliminates the defect states that cause charge carrier trapping, thereby reducing flicker noise and RTN while maintaining acceptable layout density
Solution Approach 2:
The patent applies different spatial relationships between the gate electrode and STI structure: the gate overlaps the main body of the STI for good electrical characteristics but deliberately avoids overlapping the corner regions. This local differentiation allows the gate to benefit from STI proximity where harmful effects are absent while excluding regions where defect states would degrade performance
2Object-generated harmful factors
If source/drain regions are spaced from STI corners to reduce charge carrier trapping, then flicker noise and RTN are reduced, but device area increases
Solution Approach 1:
The gate electrode serves as an intermediary structure that mediates the relationship between source/drain regions and STI corners. By positioning the gate to avoid STI corners, the patent indirectly protects source/drain regions from the harmful effects of corner defect states without requiring direct spatial separation, thus reducing device area while still minimizing charge carrier trapping
3Reliability
If silicide blocking structure is added to prevent short circuits, then device reliability is improved, but manufacturing complexity increases
Solution Approach 1:
The silicide blocking structure is merged with the existing STI structure, forming an integrated component that serves dual functions: electrical isolation and silicide formation prevention. This consolidation reduces the number of separate manufacturing steps and structures needed, thereby improving reliability without proportionally increasing manufacturing complexity
Data Source
AI summary
In some embodiments, a semiconductor device is provided. The semiconductor device includes an isolation structure disposed in a semiconductor substrate, where an inner perimeter of the isolation structure demarcates a device region of the semiconductor substrate. A gate is disposed over the device region, where an outer perimeter of the gate is disposed within the inner perimeter of the isolation structure. A first source/drain region is disposed in the device region and on a first side of the gate. A second source/drain region is disposed in the device region and on a second side of the gate opposite the first side. A silicide blocking structure partially covers the gate, partially covers the first source/drain region, and partially covers the isolation structure, where a first sidewall of the silicide blocking structure is disposed between first opposite sidewalls of the gate.