FET Contact Via Layout With Sub-Lithographic Gate Spacing
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Solution Overview
Problem
The minimum lateral spacing between gate and source/drain contact via structures in field effect transistors is limited by lithographic constraints, hindering further scaling of the transistors.
Innovation Solution
The formation of contact via structures with sub-lithographic lateral spacing is achieved by creating a gate stack structure with a gate dielectric and gate electrode, along with active-region and connection via structures, allowing for reduced lateral dimensions through separate lithographic patterning of these components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the lithographic tool capability is used to define minimum lateral spacing, then the via cavities can be formed without merging, but the lateral size of the field effect transistor cannot be reduced further
Solution Approach 1:
The contact via structure is divided into two separate formation processes: first forming the gate contact via structure, then forming the source/drain contact via structures in a subsequent lithographic step. This segmentation allows each via structure to be formed with independent precision control, enabling sub-lithographic lateral spacing while maintaining manufacturing precision for via cavity separation.
Solution Approach 2:
The patent utilizes vertical stacking of contact via structures at different lateral positions, where the gate contact via structure and source/drain contact via structures are formed in separate lithographic layers. This dimensional approach allows the lateral spacing to be smaller than the lithographic resolution limit while still ensuring via cavities do not merge during formation.
2Reliability
If the minimum lateral spacing design rule is imposed, then the via cavities remain separated, but the transistor lateral dimensions are constrained
Solution Approach 1:
The contact via formation process is segmented into distinct lithographic steps: gate contact via structures are formed first, followed by source/drain contact via structures in a second step. This segmentation removes the need for a conservative minimum lateral spacing design rule, as each via structure is formed with precise control independent of the other, thereby improving transistor scaling capability while maintaining via cavity separation reliability.
Solution Approach 2:
The gate contact via structures are formed in advance before the source/drain contact via structures. This preliminary action allows the subsequent lithographic step to focus solely on forming source/drain vias with precise lateral positioning, eliminating the need to account for gate via dimensions in the spacing calculation and enabling more aggressive transistor scaling.
Data Source
AI summary
A transistor includes a first active region and a second active region separated by a semiconductor channel, a gate stack structure including a gate dielectric and a gate electrode overlying the semiconductor channel, a gate contact via structure overlying and electrically connected to the gate electrode and having a top surface located in a first horizontal plane, a first active-region contact via structure overlying and electrically connected to the first active region, and having a top surface located within a second horizontal plane that underlies the first horizontal plane, a first connection line structure contacting a top surface of the first active-region contact via structure, and a first connection via structure contacting a top surface of the first connection line structure and having a top surface within the first horizontal plane.