Non-Planar FET Sub Spacer Fin Height Control
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Solution Overview
Problem
Current planar transistors fail to meet the requirements of miniaturization, high integration, high performance, and low power consumption due to challenges in controlling the height of the fin structure in Fin-FETs, leading to quality issues.
Innovation Solution
A non-planar FET structure with a sub spacer only on the middle sidewall of the fin structure, allowing precise control of the channel length through the formation of a sub spacer in the concave part or as a wing-like structure, which improves the fin structure's geometry and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If conventional Fin-FET structure with HF etching is used, then miniaturization and high integration are achieved, but the height of fin structure becomes hard to control
Solution Approach 1:
A sub-spacer is introduced as an intermediary element between the fin structure and the gate electrode. This sub-spacer serves as a precise positioning reference that defines the gate length, thereby indirectly controlling the fin structure dimensions with high precision without requiring direct control of the etching process
Solution Approach 2:
The sub-spacer is formed in advance before the gate electrode deposition. By pre-forming this reference structure, the subsequent gate patterning can be precisely aligned, ensuring accurate fin structure dimensions are maintained throughout the manufacturing process
2Manufacturing precision
If sub spacer is formed only on middle sidewall of fin structure, then channel length control is improved, but device structure complexity increases
Solution Approach 1:
Instead of forming sub-spacers uniformly on all sidewalls, the invention applies sub-spacers only on the middle sidewall of the fin structure. This localized approach provides sufficient channel length control while minimizing the added structural complexity and maintaining manufacturing feasibility
Data Source
AI summary
The present invention provides a non-planar FET which includes a substrate, a fin structure, a sub spacer, a gate, a dielectric layer and a source/drain region. The fin structure is disposed on the substrate. The sub spacer is disposed only on a middle sidewall of the fin structure. The gate is disposed on the fin structure. The dielectric layer is disposed between the fin structure and the gate. The source/drain region is disposed in the fin structure. The present invention further provides a method of forming the same.