III-V FET Substrate Transfer via Metal Layer
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Solution Overview
Problem
The manufacturing of III-V FETs, such as GaN HEMTs, on Si substrates faces challenges due to lattice mismatches, leading to structural defects and increased costs, which affect the yield and performance of integrated circuits.
Innovation Solution
A semiconductor circuit structure where a III-V material layer is attached to a handle substrate via a metal layer, allowing for a thinner GaN buffer layer and improved electrical properties by reducing lattice mismatch defects and enhancing heat dissipation, with a metal layer connected to the source electrode through a via for better electrical conductivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a thick GaN buffer layer (at least 4 μm) is formed on Si substrate to achieve 600V breakdown voltage, then the electrical performance is improved, but physical defects increase due to lattice mismatch
Solution Approach 1:
The patent introduces a handle substrate as an intermediary component between the GaN buffer layer and the final device structure. The GaN buffer layer is grown on Si substrate, then transferred to the handle substrate which provides mechanical support and allows removal of the defective Si substrate. This mediator approach enables achieving thick buffer layers for high breakdown voltage while isolating the device from the lattice-mismatch-induced defects at the Si/GaN interface.
Solution Approach 2:
The patent segments the device structure into distinct functional layers: the GaN buffer layer grown on Si substrate, the handle substrate for mechanical support, and the active device region. This segmentation allows the buffer layer to be optimized for electrical performance (thickness for breakdown voltage) while the handle substrate handles mechanical stability, and the defective Si substrate can be removed without affecting the final device structure.
2Reliability
If GaN buffer layer thickness is increased to achieve desired electrical properties, then breakdown voltage is improved, but manufacturing yield decreases due to defect propagation
Solution Approach 1:
The handle substrate acts as a mediator that enables the use of thick GaN buffer layers for high breakdown voltage while allowing the defective Si substrate to be removed. This process improvement increases manufacturing yield by enabling better defect management without compromising the electrical performance achieved through sufficient buffer layer thickness.
Solution Approach 2:
The patent extracts and removes the defective Si substrate after the GaN buffer layer has been grown to the required thickness. By taking out the problematic Si substrate that causes lattice mismatch defects, the manufacturing process achieves both the desired electrical properties from the thick buffer layer and improved yield by eliminating the source of defect propagation.
3Ease of manufacture
If GaN layer is grown directly on Si substrate, then manufacturing process is simplified, but lattice mismatch creates structural defects
Solution Approach 1:
The handle substrate serves as an intermediary that maintains process simplicity while improving structural quality. The GaN buffer layer is still grown on Si substrate (maintaining ease of manufacture), but the handle substrate enables subsequent removal of the defective Si substrate and transfer to a cleaner support structure, thereby improving structural quality without significantly complicating the overall manufacturing process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in higher yield, lower manufacturing costs, and superior electrical properties, including increased breakdown voltage, by minimizing defects and improving electrical connections in III-V FETs.
Implementation Method 1
enhancing heat dissipation
Implementation Method 2
metal layer connected to the source electrode through a via for better electrical conductivity
Data Source
AI summary
A method of manufacturing a III-V semiconductor circuit; the method comprising: forming a first layer of a III-V material on a growth substrate; forming a second layer of a III-V material on the first layer of III-V material; forming a FET transistor having a source electrode and a drain electrode in contact with a top surface of the second layer of a III-V material; forming a top dielectric layer above the FET transistor; forming a metal layer above the top dielectric layer, wherein said metal layer is connected to said source electrode; attaching a handle substrate to a top surface of the metal layer; removing the growth substrate from the bottom of the first layer of a III-V material; and forming a bottom dielectric layer on the bottom of the first layer of a III-V material.