FET Substrate Trimming for Buried Power Rail Via Insulation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Forming electrical contacts to buried power rails in integrated chips is complicated by the risk of shorts to other structures, which decreases the areal density of the chip due to the need for spacing, and existing via structures do not provide adequate insulation.
Innovation Solution
Thinning the substrate to position the via closer to the source/drain region while using dielectric materials to create additional space and insulate the via from the substrate, allowing the via to touch the sidewalls of the source/drain region without risking shorts, and forming a buried power rail in contact with the electrical contact.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the via is positioned closer to the source/drain region to increase areal density, then the areal density of the chip is improved, but the risk of shorts to other structures increases
Solution Approach 1:
A dielectric material is introduced as an intermediary between the via and the substrate. This dielectric layer physically separates the conductive via from the semiconductor substrate, preventing direct electrical contact and potential shorts while allowing the via to be positioned closer to the source/drain region for improved areal density.
Solution Approach 2:
The solution moves the insulation approach from a planar (2D) spacing constraint to a vertical (3D) dimension by introducing a dielectric layer beneath the via. This allows horizontal proximity for density while maintaining vertical separation for electrical isolation, effectively resolving the contradiction through dimensional transition.
2Reliability
If spacing is increased to prevent shorts, then the reliability is improved, but the areal density of the chip decreases
Solution Approach 1:
The dielectric material serves as a mediator that provides reliable electrical insulation between the via and substrate without requiring increased horizontal spacing. This intermediary layer enables high areal density while maintaining high reliability through effective electrical isolation.
3Ease of manufacture
If existing via structures are used without substrate thinning, then the manufacturing process is simpler, but the via cannot be positioned close to the source/drain region without risking shorts
Solution Approach 1:
The substrate is thinned in advance (preliminary action) before via formation, creating the necessary space for the via to be positioned close to the source/drain region. This preliminary substrate modification enables subsequent via placement that would otherwise risk shorts, achieving high areal density while maintaining reliability through the combined effect of thinning and dielectric insertion.
Data Source
AI summary
Semiconductor devices and methods of forming the same include a semiconductor base having a first width. A semiconductor device over the semiconductor base has a second width that is greater than the first width. A power rail is beneath the semiconductor base. A conductive contact extends from a top of the semiconductor device to the power rail.