FET Switch Buffer Isolation for Leakage Compensation
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Solution Overview
Problem
Solid state switches, particularly MOS devices, suffer from parasitic capacitance and current leakage that negatively impact measurement accuracy and efficiency, especially in high voltage precision instruments.
Innovation Solution
A circuit configuration is introduced that includes a first FET in series with a second FET and a buffer, where the buffer's output is coupled to the isolation terminal of one or both FETs, isolating parasitic capacitance and leakage from the signal path, using a unity gain buffer, voltage follower, or cascade complementary source follower to minimize voltage differences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a solid state switch is used in precision measurement apparatus, then switching functionality is provided, but parasitic capacitance and leakage current reduce measurement accuracy
Solution Approach 1:
The patent extracts and isolates the parasitic capacitance from the signal path by introducing a buffer circuit that couples to the isolation terminal of the FET. This separates the harmful capacitive effect from the measurement path, allowing the FET to function as a switch while its parasitic capacitance is diverted to the buffer, thereby improving measurement accuracy.
Solution Approach 2:
The buffer circuit serves as an intermediary between the FET and the measurement apparatus. It mediates the interaction by providing a low-impedance path for the parasitic capacitance current, preventing it from affecting the measurement while allowing the FET to maintain its switching function.
2Speed
If a solid state switch with large capacitance is used, then switching capability is provided, but the speed of high frequency AC components is limited
Solution Approach 1:
The patent extracts the parasitic capacitance effect from the signal path by coupling the buffer to the isolation terminal. This removes the capacitance limitation from the high-frequency signal path, allowing AC components to pass through the FET switch at higher speeds without being slowed by capacitive effects.
3Use of energy by moving object
If a solid state switch with large leakage current is used, then switching functionality is provided, but power efficiency is reduced
Solution Approach 1:
The buffer circuit acts as an intermediary that handles the leakage current from the FET's isolation terminal. By providing a dedicated path for this current through the buffer, the leakage is prevented from affecting the measurement apparatus and power consumption is reduced, improving overall power efficiency.
Data Source
AI summary
A new field-effect transistor (FET) based switch for use in/with high voltage precision instruments is provided. The switch can enable leakage compensation. A switch comprises a first FET in series with a second FET, and a buffer with an output terminal and an input terminal. The drain terminal of the first FET is connected to the source terminal of the second FET. The input terminal is coupled to the drain terminal of the second FET. At least one of: the first FET has an isolation terminal and the output terminal of the buffer is coupled to the isolation terminal of the first FET; and, the second SFET has an isolation terminal and the output terminal of the buffer is coupled to the isolation terminal of the second FET.