Bi-Directional FET Switch Circuit for Low Leakage Measurement Paths
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Solution Overview
Problem
Solid state switches, particularly field-effect transistors (FETs), experience significant current leakage which affects power efficiency and measurement accuracy in precision instruments.
Innovation Solution
A bi-directional solid state switch design comprising FETs in series with buffers configured to provide a current source to the bulk terminal, reducing leakage by maintaining a voltage equal to the drain voltage, thereby minimizing current leakage through parasitic diodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a solid state switch is used to control current flow, then switching capability and control functionality are improved, but current leakage increases which reduces power efficiency and measurement accuracy
Solution Approach 1:
A buffer circuit is introduced as an intermediary component between the control signal source and the bulk terminal of the FET. This buffer acts as a mediator that provides the necessary current to the bulk terminal without allowing leakage current to flow through the switch terminals, thus enabling switching capability while minimizing energy loss.
Solution Approach 2:
The voltage at the bulk terminal is dynamically adjusted to match the drain voltage through the buffer circuit. By changing the bulk terminal voltage parameter to follow the drain voltage, the potential difference across parasitic diodes is minimized, thereby reducing leakage current while maintaining switching functionality.
2Extent of automation
If a solid state switch is used in precision measurement apparatus, then measurement automation and control are improved, but measurement accuracy deteriorates due to leakage current
Solution Approach 1:
The buffer serves as an intermediary that isolates the measurement circuit from leakage effects. It provides the bulk terminal with the appropriate voltage without introducing leakage current into the measurement path, thus enabling automated control while preserving measurement accuracy.
Solution Approach 2:
The buffer ensures that the bulk terminal voltage matches the drain voltage, creating an equipotential condition that eliminates voltage differences across parasitic diodes. This reduces leakage current to minimal levels, thereby maintaining high measurement precision in automated measurement systems.
3Device complexity
If the bulk terminal is left floating or connected directly to source, then device complexity is reduced, but leakage current increases significantly
Solution Approach 1:
Instead of directly connecting the bulk terminal to the source or leaving it floating, a buffer is introduced as an intermediary component. This adds minimal complexity to the circuit while effectively controlling the bulk terminal voltage to minimize leakage current, representing a trade-off that favors performance over simplicity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed design effectively reduces current leakage, enhancing power efficiency and measurement accuracy in precision instruments by eliminating or greatly reducing leakage currents at the input and output terminals.
Implementation Method 1
minimizing current leakage through parasitic diodes
Data Source
AI summary
A solid state switch, comprising a first field-effect transistor (FET). The first FET has a first terminal, a second terminal, a bulk terminal and a gate terminal, and is configured to be switched between an on-state and an off-state. The solid state switch also comprises a second FET in series with the first FET. The second FET has a first terminal, a second terminal, a bulk terminal, and a gate terminal. The second terminal of the first FET is connected to the second terminal of the second FET. The solid state switch comprises a first buffer comprises an output terminal coupled to the bulk terminal of the first FET, and an input terminal coupled to the first terminal of the first FET.