T-Shaped Gate Field Effect Transistor Fabrication
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Solution Overview
Problem
Conventional methods for fabricating nitride semiconductor field effect transistors with T-shaped gate electrodes require electron-beam exposure, leading to high costs and poor reproducibility, and result in large parasitic resistance and leakage currents, limiting their high-frequency performance.
Innovation Solution
A method involving a T-shaped gate electrode sandwiched between semiconductor layers with an insulating oxide film on the inner walls of the gate opening, allowing for shorter gate lengths and reduced leakage currents, formed without electron-beam exposure, using a multilayer semiconductor structure and selective oxidation to control the insulating film thickness and coverage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If electron-beam exposure is used to fabricate T-shaped gate electrodes, then gate length can be reduced, but manufacturing cost increases and reproducibility deteriorates
Solution Approach 1:
The patent replaces the electron-beam lithography system with a simpler photolithography or direct patterning system. The T-shaped gate electrode structure is achieved through a two-step metallization process (forming gate electrode and contact electrode separately) rather than requiring complex electron-beam exposure, thereby reducing manufacturing cost and improving reproducibility while maintaining short gate length
Solution Approach 2:
The gate electrode structure is segmented into two distinct parts: the gate electrode (first electrode) and the contact electrode (second electrode). This segmentation allows each electrode to be formed independently with optimized dimensions and materials, enabling short gate length without requiring complex single-step patterning processes
2Ease of manufacture
If conventional gate electrode structures are used, then manufacturing process is simpler, but parasitic resistance increases and high-frequency characteristics deteriorate
Solution Approach 1:
The electrode structure is divided into a gate electrode and a contact electrode as separate components. The gate electrode can be optimized for low resistance and high-frequency performance, while the contact electrode handles current input/output. This segmentation reduces parasitic resistance in the gate region without complicating the overall manufacturing process
Solution Approach 2:
Different regions of the electrode structure are assigned different properties: the gate electrode region is designed with specific dimensions and materials to minimize parasitic resistance and capacitance, while the contact electrode region is optimized for current carrying capacity. This local optimization reduces harmful parasitic effects without requiring complex manufacturing
3Speed
If gate length is reduced to improve high-frequency characteristics, then maximum oscillation frequency increases, but parasitic resistance and leakage current become more significant
Solution Approach 1:
By separating the gate electrode from the contact electrode, the patent enables independent optimization of the gate region for high-frequency performance (short gate length) while the contact electrode handles current transmission. This segmentation isolates the high-frequency active region from parasitic resistance sources in the current path
Solution Approach 2:
The gate electrode acts as an intermediary between the control signal and the channel, with its optimized geometry and material properties minimizing parasitic resistance and capacitance. The separate contact electrode serves as an intermediary for current input/output, preventing leakage current paths from affecting the gate control signal
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the fabrication of field effect transistors with improved high-frequency characteristics, reduced series resistance, and increased carrier mobility, achieving better performance and reliability by eliminating the need for electron-beam lithography and enhancing reproducibility.
Implementation Method 1
an insulating oxide film on the inner walls of the gate opening
Implementation Method 2
charges are produced on the hetero junction interface on the (0001) plane through spontaneous polarization and piezo polarization
Data Source
AI summary
A field effect transistor includes a first semiconductor layer made of a multilayer of a plurality of semiconductor films and a second semiconductor layer formed on the first semiconductor layer. A source electrode and a drain electrode are formed on the second semiconductor layer to be spaced from each other. An opening having an insulating film on its inner wall is formed in a portion of the second semiconductor layer sandwiched between the source electrode and the drain electrode so as to expose the first semiconductor layer therein. A gate electrode is formed in the opening to be in contact with the insulating film and the first semiconductor layer on the bottom of the opening.