1T2R FET Unit Cells for Neuromorphic Computing
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Solution Overview
Problem
Current neuromorphic computing technologies face challenges in efficiently integrating field-effect transistors (FET) with resistive random-access memory (ReRAM) units to accelerate deep neural network (DNN) training, particularly in tightly scaled architectures that require controlled filament formation and minimal space consumption.
Innovation Solution
The integration of a 1T2R FET unit cell structure, where a field-effect transistor independently controls currents through two ReRAM units positioned on opposite sides, utilizing extrinsic semiconductor layers and nanosheet stacks to facilitate electrical isolation and efficient communication, allowing for compact and efficient neuromorphic computing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If FET is integrated with ReRAM units in tightly scaled architecture, then space consumption is reduced, but control precision over filament formation becomes difficult
Solution Approach 1:
The patent divides the semiconductor structure into separate extrinsic semiconductor layers, with each layer containing either a ReRAM unit or the FET. This segmentation allows independent control and optimization of filament formation in each layer while maintaining tight scaling, resolving the contradiction between reduced space consumption and control precision.
Solution Approach 2:
The patent applies different doping types (n-type or p-type) to different extrinsic semiconductor layers, creating locally optimized regions. The FET is formed in one layer while ReRAM units are formed in separate layers with complementary doping, enabling precise control of filament formation locally while achieving overall compact integration.
2Device complexity
If FET controls multiple ReRAM units, then device complexity is reduced, but electrical isolation between units becomes challenging
Solution Approach 1:
The patent moves the ReRAM units into a vertical dimension by forming them in separate extrinsic semiconductor layers above or below the FET layer. This three-dimensional arrangement allows the single FET to control multiple ReRAM units while maintaining electrical isolation through the layered structure, reducing device complexity without compromising isolation.
Solution Approach 2:
The patent introduces intrinsic semiconductor layers as intermediaries between the FET and ReRAM units. These intrinsic layers provide electrical isolation while allowing controlled current flow when the FET is activated, enabling the FET to control multiple ReRAM units independently without direct electrical interference between them.
3Manufacturing precision
If extrinsic semiconductor layers are used for FET and ReRAM, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The patent uses the same extrinsic semiconductor layer formation process to create both the FET active regions and the ReRAM unit structures. By forming multiple extrinsic layers with different doping types that can serve multiple functions (FET channels, ReRAM electrodes, isolation regions), the manufacturing precision is improved while the overall device complexity is managed through process integration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration accelerates DNN training by enabling independent control of ReRAM units with minimal space usage, enhancing the representation of artificial synaptic weights and improving the efficiency of neuromorphic computing applications.
Implementation Method 1
The field-effect transistor can control electrical communication between the first resistive random-access memory and a first metal contact
Data Source
AI summary
Techniques regarding FET 1T2R unit cells are provided. For example, one or more embodiments described herein can comprise a system, which can comprise a first resistive random-access memory unit operably coupled to a field-effect transistor by a first extrinsic semiconductor layer. The system can also comprise a second resistive random-access memory unit operably coupled to the field-effect transistor by a second extrinsic semiconductor layer.