On-Chip FET Variability Measurement Circuit Using Sequential Gate Energization
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Solution Overview
Problem
As semiconductor technology advances, field effect transistors (FETs) in CMOS technology become smaller, leading to undesired variations in electrical characteristics due to fabrication biases and impurity implants, affecting the accuracy of static random access memory (SRAM) and timing in digital circuits, and current methods for measuring these variations are time-consuming and inefficient, consuming significant silicon area.
Innovation Solution
An electronic circuit design that includes a plurality of FETs to be tested, a measuring FET, and a state machine to sequentially energize the gates, allowing for on-chip measurement of device variability by comparing output voltage to a reference value, enabling rapid digital data acquisition with minimal silicon area usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If external test equipment is used to measure I-V curves of individual devices, then measurement precision is improved, but measurement time increases and silicon area consumption increases
Solution Approach 1:
The patent combines multiple measurement functions into a single on-chip test circuit that can measure multiple devices simultaneously. The test circuit integrates stimulus generation, response measurement, and data processing capabilities within the chip itself, eliminating the need for external test equipment and sequential measurement of individual devices.
Solution Approach 2:
The on-chip test circuit is designed to measure multiple device types (e.g., different transistor sizes, different circuit configurations) using a single universal test structure. The circuit can selectively activate different device under test (DUT) configurations through control signals, making the test circuit applicable to various measurement scenarios without requiring separate external equipment for each case.
2Measurement precision
If external test equipment with probe pads is used for measurement, then measurement precision is improved, but silicon area per device increases
Solution Approach 1:
The patent merges the test circuit functionality directly into the chip substrate, sharing probe pads and measurement infrastructure across multiple devices. Instead of dedicating large probe pad areas to each individual device measurement, the test circuit reuses common test structures and signal paths, significantly reducing the silicon area required per measured device.
Solution Approach 2:
The measurement system is self-contained on-chip, with the test circuit generating its own test signals and processing its own measurement data without requiring external test equipment. This self-service capability eliminates the need for large external probe pad structures and reduces the overall silicon area footprint required for measurement functionality.
3Productivity
If ring oscillators are used to measure average threshold voltage, then measurement time is reduced, but measurement precision deteriorates
Solution Approach 1:
The patent introduces an intermediary measurement approach that uses carefully designed test circuits as mediators between the devices under test and the measurement system. These intermediary circuits provide precise voltage and current control while enabling rapid measurement through digital readout mechanisms, bridging the gap between the speed of ring oscillators and the precision of traditional I-V curve measurements.
4Area of stationary object
If memory operation is used to measure threshold variation of 4 or 6 devices, then measurement area is reduced, but measurement precision deteriorates due to averaging
Solution Approach 1:
The patent segments the measurement process to enable independent measurement of individual devices or small groups of devices within the memory array. By dividing the measurement functionality into device-specific test circuits that can be selectively activated, the system maintains high measurement precision for individual devices while utilizing the existing memory structure, thus achieving both area efficiency and measurement accuracy.
Data Source
AI summary
An electronic circuit includes an output terminal and at least a first measuring FET. The second drain-source terminals of a plurality of FETS to be tested are interconnected with the first drain-source terminal of the first measuring FET and the output terminal. The second drain-source terminal of the first measuring FET is interconnected with a first biasing terminal. The first drain-source terminals of the FETS to be tested are interconnected with a second biasing terminal. A state machine is coupled to the gates of the FETS to be tested and the gate of the first measuring FET. The state machine is configured to energize the gate of the first measuring FET and to sequentially energize the gates of the FETS to be tested, so that an output voltage appears on the output terminal. Circuitry to compare the output voltage to a reference value is also provided.