Self-Aligned FET Via Contacts with Dissimilar Dielectric Layers
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Solution Overview
Problem
As semiconductor devices shrink, forming vertical interconnects over source/drain contacts and metal gate stacks becomes increasingly challenging due to reduced processing windows and increased complexity, leading to potential overlay errors and higher production costs.
Innovation Solution
A method is developed to form via contact features using a patterned masking element that exposes multiple device-level features, combined with dissimilar dielectric material layers to enhance etching selectivity, allowing for self-aligned formation of via contact features that ensure sufficient contact area and reduce production complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If typical methods of forming vertical interconnects are used at smaller length scales, then processing window increases and production costs decrease, but manufacturing precision deteriorates due to reduced contact area and increased overlay errors
Solution Approach 1:
The method performs preliminary actions by forming mandrel features and dielectric layers before the actual via contact formation. The mandrel features are prepared in advance with specific patterns that guide subsequent etching processes, ensuring precise contact area formation before the critical via fabrication step occurs.
Solution Approach 2:
Mandrel features serve as intermediary structures that mediate between the lithography pattern and the final via contact geometry. These intermediate mandrels enable precise control of via contact area by acting as templates during the etching process, resolving the conflict between precision and ease of manufacture.
2Productivity
If feature sizes continue to decrease to increase functional density, then productivity increases, but manufacturing precision deteriorates due to challenges in forming vertical interconnects
Solution Approach 1:
The invention transitions from direct top-down via formation to a multi-dimensional approach using mandrel features that extend in the lateral dimension. This allows via contacts to be formed with precise dimensional control by leveraging the mandrel's lateral extent as a template, enabling accurate vertical interconnect formation at smaller feature sizes.
Solution Approach 2:
The method changes the controlling parameter for via contact dimensions from direct lithographic patterning to mandrel-based dimensional control. By using mandrel feature dimensions as the primary control parameter, the process achieves better precision at scaled dimensions where direct lithography becomes less accurate.
3Reliability
If conventional via formation methods are used, then device performance is maintained, but overlay errors increase leading to reduced manufacturing precision
Solution Approach 1:
The mandrel features enable a self-aligned formation process where the via contacts automatically align to the mandrel patterns without requiring additional overlay operations. The mandrels serve as self-referencing templates that guide via formation, eliminating the need for separate alignment steps and reducing overlay errors while maintaining device performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the formation of via contact features, reducing overlay errors and production costs while maintaining device performance by ensuring adequate contact area between via contact features and device-level features.
Implementation Method 1
portions of the second dielectric layer are removed. The second dielectric layer is different from the first dielectric layer in composition
Data Source
AI summary
A method includes providing a semiconductor structure having metal gate structures (MGs), gate spacers disposed on sidewalls of the MGs, and source/drain (S/D) features disposed adjacent to the gate spacers; forming a first dielectric layer over the MGs and forming S/D contacts (MDs) over the S/D features; forming a second dielectric layer over the first dielectric layer, where portions of the second dielectric layer contact the MDs and the second dielectric layer is different from the first dielectric layer in composition; removing the portions of the second dielectric layer that contact the MDs; forming a conductive layer over the MDs and over the first dielectric layer; and removing portions of the conductive layer to form conductive features over the MDs.