FET Package Wire-Bond Layout for Low Parasitic Inductance
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Solution Overview
Problem
Existing integrated circuit (IC) packages with field effect transistors (FETs) face challenges in managing parasitic inductance and switching noise, particularly at high switching rates, which affect performance in applications requiring high-frequency operation.
Innovation Solution
The IC package design incorporates a matrix of interleaving source and drain pads with drain and source wire bonds that form partial antiparallel loops, reducing parasitic inductance by configuring the wire bonds to avoid direct contact with the die, thereby forming a loop that minimizes parasitic inductance and switching noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If conventional wire bond configurations are used to connect FET pads to interconnect platforms, then the structure is simple and easy to manufacture, but parasitic inductance increases and switching noise worsens at high frequencies
Solution Approach 1:
The wire bond configuration is segmented into multiple sections: a first wire bond section connecting the first pad to the first platform, and a second wire bond section connecting the second pad to the second platform. This segmentation allows each section to be optimized independently for minimal inductance, with sections arranged in a coplanar configuration rather than a single continuous bond, thereby reducing overall parasitic inductance while maintaining manufacturing feasibility.
2Productivity
If high switching rates are used to improve performance, then operational efficiency increases, but switching noise increases and parasitic inductance effects worsen
Solution Approach 1:
The patent converts the harmful effect of high switching rates generating noise into a benefit by designing a wire bond configuration that is inherently noise-resistant. The coplanar arrangement of wire bond sections with optimized spacing and geometry transforms the high-frequency signal path into one that minimizes electromagnetic interference and radiated noise, allowing high switching rates to be maintained without proportionally increasing switching noise.
Data Source
AI summary
An IC package includes an interconnect having a first platform and a second platform that are spaced apart. The IC package includes a die superposing a portion of the first platform of the interconnect. The die has a field effect transistor (FET), and a matrix of pads for the FET situated on a surface of the die. The matrix of pads having a row of source pads and a row of drain pads. A drain wire bond extends from a first drain pad to a second drain pad of the row of drain pads and to the first platform of the interconnect. A source wire bond extends from a first source pad to a second source pad of the row of source pads, back over the first source pad and is coupled to a connection region of the first platform.