Fetch Reissue Queue for Processor Cache Miss Latency
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Solution Overview
Problem
Current processor systems face latency issues due to cache misses, as reissuing micro-operations from the issue queue can be delayed even after data is available in pipeline registers, leading to suboptimal performance.
Innovation Solution
Implementing a fetch reissue queue that overrides the normal issue selection algorithm to reissue micro-operations at the exact cycle when data is available in pipeline registers, bypassing the L1 cache, thereby reducing latency and improving processor performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If micro-operations are reissued from the issue queue after a cache miss, then the processor can resume execution, but latency is increased due to delayed reissuing even after data is available in pipeline registers
Solution Approach 1:
The issue queue is segmented into a main issue queue and a fetch reissue queue. The fetch reissue queue specifically handles micro-operations that need to be reissued after cache misses, separating them from the main issue queue. This segmentation allows the fetch reissue queue to override the normal issue selection algorithm and reissue micro-operations immediately when data is available in pipeline registers, reducing reissue latency without affecting the overall issue queue operation.
Solution Approach 2:
The system performs preliminary action by checking data availability in pipeline registers before the traditional cache read process completes. When data is detected in the pipeline registers, the fetch reissue queue is immediately activated to reissue the stalled micro-operations, bypassing the normal cache read latency. This preliminary detection and immediate reissue action reduces the effective latency experienced by the processor.
2Productivity
If the normal issue selection algorithm is used, then micro-operations are issued in order, but reissuing is delayed even when data is available, leading to suboptimal performance
Solution Approach 1:
The issue selection algorithm is made dynamic by allowing the fetch reissue queue to override the normal algorithm when specific conditions are met (data available in pipeline registers). The system dynamically switches between the normal issue selection algorithm and the fetch reissue queue's prioritized reissue mechanism, optimizing performance based on real-time data availability without compromising the ordered execution guarantee.
3Reliability
If data is read through the L1 cache, then data is retrieved reliably, but several cycles are lost compared to reading directly from pipeline registers
Solution Approach 1:
The fetch reissue queue acts as an intermediary mechanism that enables direct access to data already present in the pipeline registers, bypassing the L1 cache read process. When data is detected in the pipeline registers, the fetch reissue queue facilitates direct retrieval without requiring the traditional L1 cache read sequence, thus reducing access time while maintaining data reliability through the controlled override mechanism.
Data Source
AI summary
In an approach, responsibility for reissuing a fetch micro-operation is allocated to a reissue queue subsequent to a cache miss corresponding to a cache and the fetch micro-operation. Responsive to higher level cache returning data to the cache, an issue selection algorithm of the issue queue is overridden to prioritize reissuing the fetch micro-operation.